公开(公告)号：US07573093B1

公开(公告)日：2009-08-11

申请号：US11927282

申请日：2007-10-29

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

公开(公告)号：US07473960B1

公开(公告)日：2009-01-06

申请号：US11927265

申请日：2007-10-29

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20080093654A1

公开(公告)日：2008-04-24

申请号：US11962615

申请日：2007-12-21

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。