公开(公告)号：US07538379B1

公开(公告)日：2009-05-26

申请号：US11303865

申请日：2005-12-16

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

公开(公告)号：US07898018B2

公开(公告)日：2011-03-01

申请号：US12359481

申请日：2009-01-26

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

公开(公告)号：US20100038697A1

公开(公告)日：2010-02-18

申请号：US12370828

申请日：2009-02-13

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20090159954A1

公开(公告)日：2009-06-25

申请号：US12359481

申请日：2009-01-26

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

公开(公告)号：US20070215935A1

公开(公告)日：2007-09-20

申请号：US11750650

申请日：2007-05-18

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US08258567B2

公开(公告)日：2012-09-04

申请号：US13037507

申请日：2011-03-01

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US08120955B2

公开(公告)日：2012-02-21

申请号：US12371483

申请日：2009-02-13

申请人： Zhigang Wang ,  Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady

发明人： Zhigang Wang ,  Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady

IPC分类号： G11C11/34

CPC分类号： H03K19/17748 ,  G11C16/0441 ,  H03K19/1776 ,  H03K19/1778

摘要： A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.

摘要翻译： 推挽式非易失性存储器阵列包括具有与p沟道易失性上拉晶体管串联的n沟道非易失性下拉晶体管的存储单元。 非易失性晶体管行线与阵列的每一行相关联，并且耦合到该行中每个n沟道非易失性下拉晶体管的控制栅极。 易失性晶体管行线与阵列的每一行相关联，并且耦合到与其相关联的行中的每个p沟道易失性上拉晶体管的控制栅极。 列线与阵列中的每个列相关联，并且与其相关联的列中的每个p沟道易失性上拉晶体管的源极耦合。

公开(公告)号：US20110147821A1

公开(公告)日：2011-06-23

申请号：US13037507

申请日：2011-03-01

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US07956404B2

公开(公告)日：2011-06-07

申请号：US12370828

申请日：2009-02-13

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20100208520A1

公开(公告)日：2010-08-19

申请号：US12371483

申请日：2009-02-13

申请人： Zhigang Wang ,  Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady

发明人： Zhigang Wang ,  Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： H03K19/17748 ,  G11C16/0441 ,  H03K19/1776 ,  H03K19/1778

摘要： A push-pull non-volatile memory array includes memory cells with an n-channel non-volatile pull-down transistor in series with a p-channel volatile pull-up transistor. A non-volatile transistor row line is associated with each row of the array and is coupled to the control gates of each n-channel non-volatile pull-down transistor in the row. A volatile transistor row line is associated with each row of the array and is coupled to the control gates of each p-channel volatile pull-up transistor in the row with which it is associated. A column line is associated with each column in the array and is coupled to the source of each p-channel volatile pull-up transistor in the column with which it is associated.

摘要翻译： 推挽式非易失性存储器阵列包括具有与p沟道易失性上拉晶体管串联的n沟道非易失性下拉晶体管的存储单元。 非易失性晶体管行线与阵列的每一行相关联，并且耦合到该行中每个n沟道非易失性下拉晶体管的控制栅极。 易失性晶体管行线与阵列的每一行相关联，并且耦合到与其相关联的行中的每个p沟道易失性上拉晶体管的控制栅极。 列线与阵列中的每个列相关联，并且与其相关联的列中的每个p沟道易失性上拉晶体管的源极耦合。