CLOCK FREQUENCY VARIATION OF A CLOCKED CURRENT CONSUMER
    21.
    发明申请
    CLOCK FREQUENCY VARIATION OF A CLOCKED CURRENT CONSUMER 有权
    时钟电流消耗的时钟频率变化

    公开(公告)号:US20070257713A1

    公开(公告)日:2007-11-08

    申请号:US11688462

    申请日:2007-03-20

    IPC分类号: H03B19/00

    摘要: A frequency regulator for varying a clock frequency of a power-supplied consumer operated in a clocked manner, wherein the frequency regulator is implemented to perform an overall variation of the clock frequency from an actual frequency to a set frequency, such that the overall variation is obtained by a plurality of clock changes, each with a different amount of change, wherein each of the respective amounts of change depends on a power change caused by the associated clock frequency change.

    摘要翻译: 一种用于改变以时钟方式操作的供电消费者的时钟频率的频率调节器,其中实施所述频率调节器以执行所述时钟频率从实际频率到设定频率的总体变化,使得所述总体变化是 通过多个时钟变化获得,每个具有不同的变化量,其中各个变化量中的每一个取决于由关联的时钟频率变化引起的功率变化。

    Reader application device
    22.
    发明授权
    Reader application device 有权
    阅读器应用程序设备

    公开(公告)号:US08905309B2

    公开(公告)日:2014-12-09

    申请号:US12045320

    申请日:2008-03-10

    IPC分类号: G06K7/00

    CPC分类号: G06K7/0008

    摘要: A communication system including a reader application device having a reader application, and a reader configured to operate under control of the reader application to allow data to be transmitted between the reader application device and a user device via the reader.

    摘要翻译: 一种包括具有读取器应用的读取器应用设备的通信系统和被配置为在读取器应用的控制下操作以便经由读取器在读取器应用设备和用户设备之间传输数据的读取器。

    MASTER-SLAVE FLIP FLOP
    24.
    发明申请
    MASTER-SLAVE FLIP FLOP 审中-公开
    主从动画片

    公开(公告)号:US20070063752A1

    公开(公告)日:2007-03-22

    申请号:US11532584

    申请日:2006-09-18

    IPC分类号: H03K3/289

    CPC分类号: H03K3/037 H03K3/013

    摘要: Master-slave flip flop including a master latch having a data input for receiving a data input signal, an inverting clock input for receiving a first clock signal, and a data output, a slave latch having a data input which is connected to the data output of the master latch, a clock input for receiving a second clock signal, and a data output for outputting an output signal, and a time delay element connects the clock input of the slave latch to the clock input of the master latch.

    摘要翻译: 主从触发器,包括具有用于接收数据输入信号的数据输入的主锁存器,用于接收第一时钟信号的反相时钟输入和数据输出,具有连接到数据输出的数据输入的从锁存器 ,用于接收第二时钟信号的时钟输入和用于输出输出信号的数据输出,并且时间延迟元件将从锁存器的时钟输入连接到主锁存器的时钟输入。