公开(公告)号：US20170214517A1

公开(公告)日：2017-07-27

申请号：US15409918

申请日：2017-01-19

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi KONDO ,  Akihide SAI ,  Masanori FURUTA

IPC: H04L7/033 ,  H04B1/16 ,  H04L7/00 ,  H03L7/08 ,  H03L7/085

CPC classification number: H04B1/16 ,  G06F1/3278 ,  H03L7/08 ,  H03L7/0802 ,  H03L2207/50

Abstract: A receiver has an oscillator to output an oscillation signal, a receiver to perform reception processing of a reception signal, a phase frequency detector to output a first signal in response to a phase and a frequency of the oscillation signal so as to generate a second signal indicating a reference phase, a differentiator to generate a third signal being a difference between the first signal and the second signal, an oscillator controller to generate a fourth signal for controlling a phase and a frequency of the oscillator, a phase initializer to output an initialization signal for synchronizing a phase of the second signal with a phase of the first signal, a trigger signal generator to output a trigger signal indicating timing with which the phase initializer outputs the initialization signal, and a power supply controller to control whether to supply a power supply voltage.

公开(公告)号：US20160380759A1

公开(公告)日：2016-12-29

申请号：US15189236

申请日：2016-06-22

Applicant: Kabushiki Kaisha Toshiba

Inventor： Satoshi KONDO ,  Akihide SAI ,  Masanori FURUTA

IPC: H04L7/033

CPC classification number: H04L7/0332 ,  H03L7/081 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0334

Abstract: A phase locked loop has an integer phase detector to detect an integer phase by measuring a cycle number, a fractional phase detector to detect a fractional phase of smaller than one cycle between a reference signal and the oscillation signal, a frequency error generator to generate a frequency error signal between the reference signal and the oscillation signal, a glitch corrector to correct the frequency error signal to generate and output a glitch-corrected signal and the frequency error signal, a phase error generator to generate a phase error by integrating an output signal of the glitch corrector, an oscillator controller to control an oscillation frequency of the oscillation signal, and a synchronous detector to detect whether a phase of the reference signal and a phase of the oscillation signal are in an phase-lock state, and to stop detection of the integer phase when the phase-lock state is detected.

Abstract translation: 锁相环具有通过测量周期数来检测整数相位的整数相位检测器，用于检测参考信号和振荡信号之间小于一个周期的分数相位的分数相位检测器，产生 参考信号和振荡信号之间的频率误差信号，毛刺校正器，用于校正频率误差信号以产生和输出毛刺校正信号和频率误差信号;相位误差发生器，用于通过对输出信号进行积分来产生相位误差 干扰校正器的振荡器控制器，用于控制振荡信号的振荡频率的振荡器控制器，以及用于检测参考信号的相位和振荡信号的相位是否处于锁相状态的同步检测器，并且停止检测 检测相位锁定状态时的整数相位。