公开(公告)号：US20160336942A1

公开(公告)日：2016-11-17

申请号：US15110912

申请日：2014-02-05

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min BAE ,  Joon-Yeong LEE

IPC: H03L7/08 ,  H03L7/18 ,  H04L7/04 ,  H03L7/07

CPC classification number: H03L7/0807 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/113 ,  H03L7/1806 ,  H04L7/04

Abstract: The CDR (Clock Data Recovery) device may include at least one or more CDR channels configured to receive input data stream; and a global clock generator configured to provide a frequency locked clock to each of the at least one or more CDR channels, wherein each of the at least one or more CDR channels creates a reference clock signal for the global clock generator.

Abstract translation: CDR（时钟数据恢复）设备可以包括被配置为接收输入数据流的至少一个或多个CDR信道; 以及全球时钟发生器，被配置为向所述至少一个或多个CDR信道中的每一个提供频率锁定时钟，其中所述至少一个或多个CDR信道中的每一个为全局时钟发生器创建参考时钟信号。

公开(公告)号：US20140269783A1

公开(公告)日：2014-09-18

申请号：US13846688

申请日：2013-03-18

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min BAE ,  Tae Hun Yoon ,  Joon Yeong Lee

IPC: H03L7/081 ,  H04J3/06

CPC classification number: H03L7/081 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0998 ,  H04J3/06

Abstract: The proposed invention is about an improved method for serial-in and serial-out transceiver applications. The proposed system includes a dual loop phase locked loop (PLL) architecture having a PLL and a phase rotator (PR)-based delay locked loop (DLL). An advantage of this architecture is that a single PLL offers decoupled bandwidths; a wide jitter-tolerance (JTOL) bandwidth for receiving data and a narrow jitter transfer (JTRAN) bandwidth for the data transmission. Thus, the amount of jitter at the output can be substantially reduced relative to the input while offering sufficient jitter tracking bandwidth. Also, this architecture is suitable for low-power applications since a phase shifter in the data path, which is one of the most power-hungry blocks in conventional DPLL designs, is not required.

Abstract translation: 所提出的发明是关于串行和串行收发器应用的改进方法。 所提出的系统包括具有PLL和基于相位旋转器（PR）的延迟锁定环（DLL）的双环路锁相环（PLL）架构。 该架构的优点是单个PLL提供去耦带宽; 用于接收数据的宽抖动容限（JTOL）带宽和用于数据传输的窄抖动传输（JTRAN）带宽。 因此，在提供足够的抖动跟踪带宽的同时，输出端的抖动量可以相对于输入显着减小。 此外，该架构适用于低功耗应用，因为数据通路中的移相器是传统DPLL设计中功耗最大的块之一。

公开(公告)号：US20140184351A1

公开(公告)日：2014-07-03

申请号：US14103005

申请日：2013-12-11

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Hyeon Min BAE ,  Ha Il SONG ,  Huxian JIN

IPC: H01P5/04 ,  H01P3/16

CPC classification number: H01P3/122 ,  H01P3/16 ,  H01P5/087 ,  H01P5/107

Abstract: An exemplary embodiment of the present invention provides an improved dielectric waveguide named electrical fiber. The electrical fiber with a metal cladding may isolate the interference of the signals in other wireless channels and adjacent electrical fibers, which typically causes band-limitation problem, for a smaller radiation loss and better signal guiding to lower the total transceiver power consumption as the transmit distance increases. Also, the electrical fiber may have frequency independent attenuation characteristics to enable high data rate transfer with little or even without any additional receiver-side compensation due to vertical coupling of the electrical fiber and an interconnection device.

Abstract translation: 本发明的示例性实施例提供了一种改进的电介质波导，称为电光纤。 具有金属覆层的电光纤可以隔离其它无线信道和相邻电缆中的信号的干扰，这通常导致带限问题，以减小辐射损耗，并且更好的信号导向以降低总的收发机功率消耗，因为传输 距离增加。 此外，电光纤可以具有频率独立的衰减特性，以便由于电光纤和互连设备的垂直耦合而很少或甚至没有任何额外的接收器侧补偿来实现高数据速率传输。