公开(公告)号：US06320215B1

公开(公告)日：2001-11-20

申请号：US09359292

申请日：1999-07-22

申请人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.

摘要翻译： 一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。 侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。 制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件 在侧壁上的刻面晶体区域上。 小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

公开(公告)号：US06614074B2

公开(公告)日：2003-09-02

申请号：US09092749

申请日：1998-06-05

申请人： Gary Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Jack A. Mandelman

发明人： Gary Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David Horak ,  Jack A. Mandelman

IPC分类号： H01L2976

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829

摘要： A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

摘要翻译： 一种带槽的平面DRAM传输装置，其具有形成在位于源极和漏极区域之间的衬底的沟槽中的带槽门。 带槽门具有侧壁部分和限定其上的通道的底部部分。 底部包括掺杂的凹穴，使得底部上的阈值电压Vt基本上小于侧壁部分上的Vt，使得侧壁部分主要控制通过该装置的电流。

公开(公告)号：US06426251B2

公开(公告)日：2002-07-30

申请号：US09894427

申请日：2001-06-28

申请人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Gary Bronner ,  Ulrike Gruening ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L27/1087 ,  H01L27/10876

摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.

摘要翻译： 一种动态随机存取存储器（DRAM）单元，其包括具有部分地设置在沟槽的侧壁上的有源晶体管器件的深沟槽存储电容器。 侧壁与具有沿着单晶轴的结晶取向的第一结晶平面对准。 制造这种DRAM单元的方法包括：（a）在衬底中形成深沟槽，（b）沿着具有单晶取向的沟槽侧壁形成刻面晶体区域，以及（c）形成部分设置的晶体管器件 在侧壁上的刻面晶体区域上。 小面晶体区域可以通过生长氧化物环形成，例如通过局部热氧化在选择的氧化条件下，以促进沿着第一晶体轴系的较高的氧化速率而不是第二晶体轴系。

公开(公告)号：US6140208A

公开(公告)日：2000-10-31

申请号：US245958

申请日：1999-02-05

申请人： Farid Agahi ,  Gary Bronner ,  Bertrand Flietner ,  Erwin Hammerl ,  Herbert Ho ,  Radhika Srinivasan

发明人： Farid Agahi ,  Gary Bronner ,  Bertrand Flietner ,  Erwin Hammerl ,  Herbert Ho ,  Radhika Srinivasan

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A reduction in parasitic leakages of shallow trench isolation vias is disclosed wherein the distance between the silicon nitride liner and the active silicon sidewalls is increased by depositing an insulating oxide layer prior to deposition of the silicon nitride liner. Preferably, the insulating oxide layer comprises tetraethylorthosilicate. The method comprises of etching one or more shallow trench isolations into a semiconductor wafer; depositing an insulating oxide layer into the trench; growing a thermal oxide in the trench; and depositing a silicon nitride liner in the trench. The thermal oxide may be grown prior to or after deposition of the insulating oxide layer.

摘要翻译： 公开了浅沟槽隔离通孔的寄生泄漏的减少，其中通过在沉积氮化硅衬垫之前沉积绝缘氧化物层来增加氮化硅衬垫和有源硅侧壁之间的距离。 优选地，绝缘氧化物层包括原硅酸四乙酯。 该方法包括将一个或多个浅沟槽隔离件蚀刻成半导体晶片; 将绝缘氧化物层沉积到沟槽中; 在沟槽中生长热氧化物; 以及在沟槽中沉积氮化硅衬垫。 热氧化物可以在沉积绝缘氧化物层之前或之后生长。