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    VTFT formation using capillary action
    3.
    发明授权
    VTFT formation using capillary action 有权
    VTFT形成使用毛细作用

    公开(公告)号：US09093470B1

    公开(公告)日：2015-07-28

    申请号：US14198621

    申请日：2014-03-06

    申请人： Shelby Forrester Nelson ,  Carolyn Rae Ellinger

    发明人： Shelby Forrester Nelson ,  Carolyn Rae Ellinger

    IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/108

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10864 ,  H01L29/66742 ,  H01L29/78642

    摘要： Producing a vertical transistor includes providing a conductive gate structure having a reentrant profile on a substrate. A conformal dielectric material layer is formed on the conductive gate structure. A conformal semiconductor material layer is formed on the dielectric material layer, over the conductive gate structure. An electrode is formed located over the conductive gate structure and in contact with a first portion of the semiconductor layer and another electrode is formed vertically separated from the electrode and located in contact with a second portion of the semiconductor layer by printing an inhibitor that wicks along the reentrant profile of the conductive gate structure and depositing a conductive inorganic thin film using an atomic layer deposition process where the inhibitor is absent to form a channel in the semiconductor layer along the reentrant profile between the electrodes by inhibiting deposition of conductive material between the electrodes with the wicked inhibitor.

    摘要翻译： 制造垂直晶体管包括提供在衬底上具有可重入分布的导电栅极结构。 在导电栅极结构上形成保形介电材料层。 在电介质材料层上，在导电栅极结构之上形成共形半导体材料层。 电极形成在导电栅极结构的上方并与半导体层的第一部分接触，而另一个电极形成为与电极垂直分离并通过印刷阻挡剂与半导体层的第二部分接触而形成 导电栅极结构的折返轮廓，并且使用原子层沉积工艺沉积导电无机薄膜，其中不存在抑制剂以通过在电极之间的凹槽轮廓在半导体层中形成通道，通过抑制导电材料在电极之间的沉积 与邪恶的抑制剂。

    Simplified buried plate structure and process for semiconductor-on-insulator chip
    6.
    发明授权
    Simplified buried plate structure and process for semiconductor-on-insulator chip 有权
    半导体绝缘体芯片的简化掩埋板结构和工艺

    公开(公告)号：US08053823B2

    公开(公告)日：2011-11-08

    申请号：US10906808

    申请日：2005-03-08

    申请人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

    发明人： Kangguo Cheng ,  Ramachandra Divakaruni ,  Herbert L. Ho ,  Carl J. Radens

    IPC分类号： H01L27/108

    CPC分类号： H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

    摘要： A structure is provided herein which includes an array of trench capacitors having at least portions disposed below a buried oxide layer of an SOI substrate. Each trench capacitor shares a common unitary buried capacitor plate which includes at least a portion of a first unitary semiconductor region disposed below the buried oxide layer. An upper boundary of the buried capacitor plate defines a plane parallel to a major surface of the substrate which extends laterally throughout the array of trench capacitors. In a particular embodiment, which starts from either an SOI or a bulk substrate, trenches of the array and a contact hole are formed simultaneously, such that the contact hole extends to substantially the same depth as the trenches. The contact hole preferably has substantially greater width than the trenches such that the conductive contact via can be formed simultaneously by processing used to form trench capacitors extending along walls of the trenches.

    摘要翻译： 本文提供了一种结构，其包括具有设置在SOI衬底的掩埋氧化物层下方的至少部分的沟槽电容器阵列。 每个沟槽电容器共享共同的单一掩埋电容器板，其包括设置在掩埋氧化物层下方的第一单一半导体区域的至少一部分。 掩埋电容器板的上边界限定平行于衬底的主表面的平面，横向延伸穿过整个沟槽电容器阵列。 在从SOI或体衬底开始的特定实施例中，阵列的沟槽和接触孔同时形成，使得接触孔延伸到与沟槽基本相同的深度。 接触孔优选地具有比沟槽更大的宽度，使得可以通过用于形成沿着沟槽的壁延伸的沟槽电容器的处理同时形成导电接触通孔。

    Field effect transistor
    7.
    发明授权
    Field effect transistor 有权
    场效应晶体管

    公开(公告)号：US07767518B2

    公开(公告)日：2010-08-03

    申请号：US12266876

    申请日：2008-11-07

    申请人： Helmut Tews

    发明人： Helmut Tews

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10841 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/10864 ,  H01L27/10876 ,  H01L29/161 ,  H01L29/4916 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/7827 ,  Y10T29/41

    摘要： A field effect transistor is provided. The field effect transistor includes a channel region, electrically conductive channel connection regions, and a control region. The electrically conductive channel connection regions adjoin the channel region along with a transistor dielectric. The control region is separated from the channel region by the transistor dielectric. In addition, the control region may comprise a monocrystalline material.

    摘要翻译： 提供场效应晶体管。 场效应晶体管包括沟道区，导电沟道连接区和控制区。 导电沟道连接区域与晶体管电介质连接在沟道区域上。 控制区域通过晶体管电介质与沟道区域分离。 此外，控制区域可以包括单晶材料。

    Vertical SOI transistor memory cell and method of forming the same
    8.
    发明授权
    Vertical SOI transistor memory cell and method of forming the same 失效
    垂直SOI晶体管存储单元及其形成方法

    公开(公告)号：US07759191B2

    公开(公告)日：2010-07-20

    申请号：US11931238

    申请日：2007-10-31

    申请人： Kangguo Cheng ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Jack A. Mandelman

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/10841 ,  H01L27/10864

    摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.

    摘要翻译： 本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。 具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。 垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。 垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。 优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

    Vertical trench memory cell with insulating ring
    9.
    发明授权
    Vertical trench memory cell with insulating ring 有权
    带绝缘环的垂直沟槽存储单元

    公开(公告)号：US07528035B2

    公开(公告)日：2009-05-05

    申请号：US11688562

    申请日：2007-03-20

    申请人： Kangguo Cheng

    发明人： Kangguo Cheng

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/1203

    摘要： A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing out diffusions from the trench memory cells.

    摘要翻译： 提供一种形成具有绝缘环的垂直晶体管沟槽存储单元的方法。 该方法包括在半导体衬底的蚀刻部分中形成半导体材料区域; 部分地蚀刻半导体材料区域以形成深沟槽，其中深沟槽延伸超过半导体材料区域，并且其中部分蚀刻的半导体材料区域的剩余部分限定绝缘环。 然后在深沟槽中形成垂直晶体管，使得垂直晶体管被绝缘环隔离。 还提供了半导体结构。 半导体结构包括形成在半导体衬底上的第一和第二沟槽存储单元; 以及围绕所述第一和第二沟槽存储单元中的每一个的绝缘环。 绝缘环被配置为显着地封闭来自沟槽存储器单元的扩散。