公开(公告)号：US20240306368A1

公开(公告)日：2024-09-12

申请号：US18593988

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Takeru MAEDA ,  Kotaro NODA ,  Shosuke FUJII

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/05

Abstract: A semiconductor device includes a semiconductor substrate, a memory capacitor provided on the semiconductor substrate, a first conductor provided above the memory capacitor and extending in a first direction, a second conductor provided above the first conductor and extending in the first direction, an oxide semiconductor layer provided between the first conductor and the second conductor and extending in the first direction, a conductive oxide layer between the second conductor and the oxide semiconductor layer, a first conductive layer between the conductive oxide layer and the second conductor, and an insulating layer in contact with the conductive oxide layer, wherein a portion of the conductive oxide layer is between and aligned with the first insulating layer and the oxide semiconductor layer in the first direction.

公开(公告)号：US20240237563A9

公开(公告)日：2024-07-11

申请号：US18396275

申请日：2023-12-26

Applicant: Kioxia Corporation

Inventor： Hiroyuki Ode ,  Kotaro NODA

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B63/80 ,  H10N70/231 ,  H10N70/826

Abstract: A semiconductor memory device includes a first wiring to a fifth wiring, a plurality of memory cells disposed between the wirings, and a first contact electrode to a third contact electrode. The first contact electrode is disposed between the first wiring and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode is disposed between the first contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The third contact electrode is disposed between the second contact electrode and the fifth wiring, and is electrically connected to the first wiring and the fifth wiring. The second contact electrode has a width larger than a width of the first contact electrode and larger than a width of the third contact electrode.

公开(公告)号：US20240090203A1

公开(公告)日：2024-03-14

申请号：US18455732

申请日：2023-08-25

Applicant: Kioxia Corporation

Inventor： Takanori AKITA ,  Kotaro NODA ,  Seiichi URAKAWA ,  Mutsumi OKAJIMA

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/33

Abstract: A semiconductor storage device includes a first oxide semiconductor layer that extends in a first direction; a second oxide semiconductor layer that extends in the first direction and is adjacent to the first oxide semiconductor layer in a second direction intersecting to the first direction; first wiring that extends in a third direction intersecting to the first direction and overlaps with the first oxide semiconductor layer in the third direction; second wiring that extends in the third direction and overlaps with the second oxide semiconductor layer in the third direction; a first insulating film that is provided between the first wiring and the first oxide semiconductor layer; a second insulating film that is provided between the second wiring and the second oxide semiconductor layer; a first conductor that is provided on the first oxide semiconductor layer; a second conductor that is provided on the second oxide semiconductor layer; and an insulating layer that has a gap between the first conductor and the second conductor or between the first wiring and the second wiring.

公开(公告)号：US20240057313A1

公开(公告)日：2024-02-15

申请号：US18179620

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Taro SHIOKAWA ,  Takeru MAEDA ,  Kotaro NODA ,  Shosuke FUJII

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/05

Abstract: A semiconductor device includes a semiconductor substrate, a first layer formed on the semiconductor substrate and including a semiconductor element and a first insulating film, a second layer formed above the first layer and including a channel including an oxide semiconductor and a second insulating film, and a third layer formed above the second layer, and including an electrode formed on the channel and a third insulating film having a film density less than at least one of a film density of the first insulating film or a film density of the second insulating film.

公开(公告)号：US20230402395A1

公开(公告)日：2023-12-14

申请号：US18331519

申请日：2023-06-08

Applicant: Kioxia Corporation

Inventor： Kotaro NODA ,  Kyoko NODA ,  Shosuke FUJII ,  Yusuke ARAYASHIKI ,  Hiroyuki ODE

IPC: H01L23/544 ,  H10B63/10 ,  H10B63/00

CPC classification number: H01L23/544 ,  H10B63/10 ,  H10B63/24 ,  H10B63/80 ,  H01L2223/54426

Abstract: A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.

公开(公告)号：US20210210556A1

公开(公告)日：2021-07-08

申请号：US17203110

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Kotaro NODA

IPC: H01L27/24 ,  H01L45/00

Abstract: A certain embodiment includes: first wiring layers extended in a first direction arranged in a second direction crossing the first direction; second wiring layers, including two layers having mutually different materials, extended in the second direction arranged in the first direction above the first wiring layers; third wiring layers extended in the first direction arranged in the second direction above the second wiring layers; a first memory cell disposed between one second wiring layer and one first wiring layer between the second and first wiring layers; a second memory cell disposed between one third wiring layer and the one second wiring layer between the third and second wiring layers; a third memory cell disposed between the one second wiring layer and another closest first wiring layer adjacent to the first wiring layer having the first memory cell; and an insulation layer disposed between the first and third memory cells.