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公开(公告)号：US5493528A
公开(公告)日：1996-02-20
申请号：US435959
申请日：1995-05-05
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
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公开(公告)号：US5448519A
公开(公告)日：1995-09-05
申请号：US294407
申请日：1994-08-23
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Mitsuru Ikegami , Tadashi Kuwabara , Hiromichi Enomoto , Tadashi Kyoda
CPC分类号： G06T1/20 , G06F7/575 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.
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23.发明授权Memory circuit formed on integrated circuit device and having programmable function 失效存储电路形成在集成电路器件上并具有可编程功能
公开(公告)号：US5175838A
公开(公告)日：1992-12-29
申请号：US349403
申请日：1989-05-08
CPC分类号： G06F7/575 , G06T1/20 , G06T1/60 , G09G5/393 , G09G2340/10
摘要： A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.
摘要翻译： 包括可以任意执行数据读取，写入和存储操作的存储器元件的存储器电路，存储元件具有二进制/算术运算功能。 在要在存储器周期中执行的读取/修改/写入模式中，并且存储来自存储器元件的数据和来自外部设备的数据的间隔中，在外部数据和存储器元件中的数据之间执行操作， 在写入周期期间存储操作结果，从而实现更高速的操作。
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公开(公告)号：US5175816A
公开(公告)日：1992-12-29
申请号：US641064
申请日：1991-01-14
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
IPC分类号： G06F9/308
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes, a second address operation unit for updating the address of data in units of a bit or multiple bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或多字节为单位更新数据单元的地址，以单字节或多字节为单位执行操作;第二地址操作单元，用于以 位或多位，地址控制装置，用于响应于由第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址;以及装置，用于获取用于操作的字节宽数据， 第一地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。
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公开(公告)号：US4849907A
公开(公告)日：1989-07-18
申请号：US848459
申请日：1986-04-07
CPC分类号： G09G5/393 , G06T11/203
摘要： In a draw processing apparatus for drawing a character, pattern or image; a segment element of a horizontal or vertical continuous run length, a coordinate of a start point of the segment and a direction coefficient of the segment are calculated, a boundary coordinate of a draw area in which a data is to be drawn is calculated in accordance with a position and a size of the draw area, a valid portion and an invalid portion of the segment are calculated for each segment element for the result first calculation result in accordance with the second calculation result, and the valid segment portion is drawn in accordance with the first calculation result.
摘要翻译： 在用于绘制字符，图案或图像的绘制处理装置中; 计算水平或垂直连续行程长度的段元素，段的开始点的坐标和段的方向系数，根据其中绘制数据的绘制区域的边界坐标 根据第二计算结果，针对结果第一计算结果针对每个段元素计算绘制区域的位置和大小，对于段的有效部分和无效部分，并根据第二计算结果绘制有效段部分 具有第一个计算结果。
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公开(公告)号：US5113487A
公开(公告)日：1992-05-12
申请号：US314238
申请日：1989-02-22
IPC分类号： G09G5/393
CPC分类号： G09G5/393 , G09G2340/10
摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in a read-modify-write mode can be used commonly.
摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写入控制数据中的一个的选择器具有选择控制信号，使得可以通常使用以读 - 修改 - 写入模式操作的帧缓冲存储器。
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公开(公告)号：US06437790B1
公开(公告)日：2002-08-20
申请号：US08487399
申请日：1995-06-07
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
IPC分类号： G09G102
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或乘法字节为单位更新数据地址，以字节或多字节为单位进行操作;第二地址操作单元，用于以位为单位更新数据的地址 或多个位，响应于第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址的地址控制装置，以及用于获取由第一地址操作单元寻址的操作的字节宽数据的装置 地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。
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28.发明授权Integrated memory circuit and function unit with selective storage of logic functions 失效集成存储器电路和功能单元，具有选择性存储逻辑功能
公开(公告)号：US5265234A
公开(公告)日：1993-11-23
申请号：US13174
申请日：1993-01-29
CPC分类号： G09G5/393 , G09G2340/10
摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.
摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写控制数据中的一个的选择器给出选择控制信号，使得可以通常使用以读 - 修改 - 写模式操作的帧缓冲存储器。
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公开(公告)号：US5034900A
公开(公告)日：1991-07-23
申请号：US779794
申请日：1985-09-24
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes. A second address operation unit for updating the address of data in units of a bit or multiple bits, an address controller operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit. Fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或多字节为单位更新数据的地址，以便以字节或多个字节为单位进行操作。 第二地址操作单元，用于以比特或多个比特为单位更新数据的地址;操作在第一地址操作单元上的地址控制器，以响应于第二地址操作单元的地址提前结果来推进地址。 获取由第一地址操作单元寻址的操作的字节宽数据，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。
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公开(公告)号：US06552730B1
公开(公告)日：2003-04-22
申请号：US08436526
申请日：1995-05-08
申请人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
发明人： Koichi Kimura , Toshihiko Ogura , Hiroaki Aotsu , Kiichiro Urabe
IPC分类号： G09G537
CPC分类号： G06F9/30018
摘要： A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或乘法字节为单位更新数据地址，以字节或多字节为单位进行操作;第二地址操作单元，用于以位为单位更新数据的地址 或多个位，响应于第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址的地址控制装置，以及用于获取由第一地址操作单元寻址的操作的字节宽数据的装置 地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。
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