利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.026 秒)

    Draw processing method and apparatus
    1.
    发明授权
    Draw processing method and apparatus 失效
    绘制处理方法和装置

    公开(公告)号：US4849907A

    公开(公告)日：1989-07-18

    申请号：US848459

    申请日：1986-04-07

    申请人： Hiroaki Aotsu ,  Toshihiko Ogura ,  Koichi Kimura ,  Tadashi Kuwabara ,  Yuuichi Makaya

    发明人： Hiroaki Aotsu ,  Toshihiko Ogura ,  Koichi Kimura ,  Tadashi Kuwabara ,  Yuuichi Makaya

    IPC分类号： G06F3/153 ,  G06F3/14 ,  G06T11/00 ,  G06T11/20 ,  G09G5/393

    CPC分类号： G09G5/393 ,  G06T11/203

    摘要： In a draw processing apparatus for drawing a character, pattern or image; a segment element of a horizontal or vertical continuous run length, a coordinate of a start point of the segment and a direction coefficient of the segment are calculated, a boundary coordinate of a draw area in which a data is to be drawn is calculated in accordance with a position and a size of the draw area, a valid portion and an invalid portion of the segment are calculated for each segment element for the result first calculation result in accordance with the second calculation result, and the valid segment portion is drawn in accordance with the first calculation result.

    摘要翻译： 在用于绘制字符，图案或图像的绘制处理装置中; 计算水平或垂直连续行程长度的段元素，段的开始点的坐标和段的方向系数，根据其中绘制数据的绘制区域的边界坐标 根据第二计算结果，针对结果第一计算结果针对每个段元素计算绘制区域的位置和大小，对于段的有效部分和无效部分，并根据第二计算结果绘制有效段部分 具有第一个计算结果。

    Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display
    2.
    发明授权
    Graphic system including a plurality of one chip semiconductor integrated circuit devices for displaying pixel data on a graphic display 失效
    图形系统包括用于在图形显示器上显示像素数据的多个单芯片半导体集成电路器件

    公开(公告)号：US5838337A

    公开(公告)日：1998-11-17

    申请号：US294406

    申请日：1994-08-23

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G06F15/76

    CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

    摘要： A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal. Further the logic circuit of the one-chip semiconductor integrated circuit device outputs pixel data based on the logic operation carried out by the logic circuit so as to display the pixel data from the logic circuit on one of the display portions of the graphic display area of the display device.

    摘要翻译： 一种包括具有包括多个显示部分和多个单芯片半导体集成电路装置的图形显示区域的显示装置的图形系统。 每个单芯片半导体集成电路包括用于存储多个像素数据的存储器，每个像素数据包括多个位和颜色数据，以及用于对从存储器读出的一个像素数据的单元执行逻辑运算的逻辑电路 基于提供给单芯片半导体集成电路器件的功能信号。 功能信号表示从存储器读出的一个像素数据的单位与由逻辑电路输出的像素数据之间的关系。 本发明还包括用于将功能信号提供给单芯片半导体集成电路器件的外部器件。 多个单芯片半导体集成电路装置的逻辑电路各自根据功能信号执行相同的逻辑运算。 此外，单芯片半导体集成电路器件的逻辑电路基于由逻辑电路执行的逻辑运算输出像素数据，以便在逻辑电路的图形显示区域的显示部分之一上显示来自逻辑电路的像素数据 显示设备。

    Memory device
    5.
    发明授权
    Memory device 失效
    内存设备

    公开(公告)号：US5617360A

    公开(公告)日：1997-04-01

    申请号：US588232

    申请日：1996-01-18

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

    CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

    摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

    摘要翻译： 形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器 用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元 以及从第二输入提供的第二数据。 操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。 从存储位置的选定部分读出第二数据。 对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。 在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。

    Memory device
    10.
    发明授权
    Memory device 失效
    内存设备

    公开(公告)号：US06359812B2

    公开(公告)日：2002-03-19

    申请号：US09750040

    申请日：2000-12-29

    申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

    IPC分类号： G11C1300

    CPC分类号： G11C11/4076 ,  G06T1/60 ,  G11C7/1006

    摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

    摘要翻译： 形成在IC芯片上的存储器件包括用于进行数据读取和写入操作的动态随机存取存储器，用于从IC芯片的外部侧接收数据的第一和第二数据端子以及具有连接到IC芯片的第一数据输入端的控制器 用于接收第一数据的数据终端，连接以接收第二数据读取的第二输入，连接到第二数据终端以接收功能模式信号的第三数据输入，以及用于执行从第一数据输入提供的第一数据之间的操作的操作单元 以及从第二输入提供的第二数据。 操作单元包括功能设置单元，其响应于在接收到第一数据之前设置由功能模式信号指示的功能的功能模式信号。 从存储位置的选定部分读出第二数据。 对于第一和第二数据执行与由功能设置单元设置的功能相对应的操作。 在一个存储器周期期间，通过动态随机存取存储器的输入将执行的结果写入存储位置的所选部分。