公开(公告)号：US4998242A

公开(公告)日：1991-03-05

申请号：US283178

申请日：1988-12-09

申请人： Daniel C. Upp

发明人： Daniel C. Upp

IPC分类号： H04Q3/52 ,  H04J3/06 ,  H04J3/16 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/0623 ,  H04J3/1611

摘要： Switching components and switching networks utilizing a plurality of identical switching components are provided for cross-connecting virtual tributaries of a plurality of substantially SONET formatted signals. The switching components each receive at least one SONET formatted signal and disassemble the signal into its virtual tributary (VT) payload components while marking the V5 byte. The VT data is buffered and switched in phase, time, and space to effect the cross-connect onto SONET signal generating output buses which are synchronously clocked buses running through the components. The space switch is essentially a non-blocking switch matrix. The time switch is a comparison means associated with each incoming VT which compares the VT destination of the data in the buffer to a virtual tributary time indication based on the phase of the synchronous clocked output buses. When the bus phase is indicative of the VT destination of the data, the data is sent to the output bus dictated by the space switch connection. Phase switching is obtained by determining the difference in phase of the incoming VT as defined by the tagged V5 byte and the phase of the synchronous clocked output bus. The phase difference permits a VT frame pointer to be correctly generated. To establish component and system operation and timing, a system bit clock and multiframe clock are provided, with the internal clock of each component in a network chain being advanced one bit clock relative to its adjacent lower component.

摘要翻译： 提供利用多个相同的切换组件的交换组件和交换网络，用于跨多个基本SONET格式化信号的虚拟支路交叉连接。 交换组件各自接收至少一个SONET格式的信号，并且在标记V5字节的同时将该信号分解成其虚拟支路（VT）有效载荷分量。 VT数据以相位，时间和空间进行缓冲和切换，以实现交错连接到产生输出总线的SONET信号上，这些输出总线是通过组件运行的同步计时总线。 空间开关本质上是一个非阻塞开关矩阵。 时间切换是与每个输入VT相关联的比较装置，其基于同步时钟输出总线的相位将缓冲器中的数据的VT目的地与虚拟支路时间指示进行比较。 当总线相位指示数据的VT目的地时，数据被发送到由空间交换机连接指定的输出总线。 通过确定由标记的V5字节和同步时钟输出总线的相位定义的输入VT的相位差来获得相位切换。 相位差允许正确生成VT帧指针。 为了建立组件和系统操作和定时，提供了系统位时钟和多帧时钟，网络链中每个组件的内部时钟相对于其相邻的下部组件提前一位。

公开(公告)号：US4967405A

公开(公告)日：1990-10-30

申请号：US283172

申请日：1988-12-09

申请人： Daniel C. Upp ,  William T. Cochran

发明人： Daniel C. Upp ,  William T. Cochran

IPC分类号： H04J3/08 ,  H04J3/16

CPC分类号： H04J3/1611 ,  H04J3/08

摘要： A modular, expandable, non-blocking system for cross-connecting high speed digital signals is provided. The system is capable of connecting DSn, CEPTn, and STSn signals as desired, with lower rate signals being included as components of the high-rate signals or terminating on low speed lines, as desired. The system accomplishes its goals by converting all incoming signals into a substantially SONET format, and by processing all the signals in that format. The signals are typically cross-connected in the substantially SONET format, although an expandable non-blocking wide band cross-connect module is provided which cross-connects any like signals. If the outgoing signal is to be in other than SONET format, the substantially SONET formatted signal is reconverted into its outgoing format. To create a complete system, various modules are utilized, including: add/drop multiplexer means for add/drop applications of DS-0, DS-1, CEPTn signals, etc.; a SONET bus interface; a virtual tributary cross-connect module which cross-connects virtual tributary payloads in space, time, and phase to generate new substantially SONET formatted signals; a wide band cross-connect module; a DS-3/SONET converter; and front end interfaces including a DS3 line interface, and various STSn interfaces. The modules may be mixed and matched as desired to accommodate a multitude of applications.

摘要翻译： 提供了用于交叉连接高速数字信号的模块化，可扩展的非阻塞系统。 该系统能够根据需要连接DSn，CEPTn和STSn信号，根据需要，较低速率信号被包括作为高速率信号的分量或终止于低速线路。 该系统通过将所有输入信号转换成基本SONET格式并通过处理该格式的所有信号来实现其目标。 尽管提供了可扩展的非阻塞宽带交叉连接模块，这些信号通常以基本上SONET格式进行交叉连接，其交叉连接任何类似的信号。 如果输出信号不是SONET格式，则基本上SONET格式的信号被转换为其输出格式。 为了创建一个完整的系统，使用了各种模块，包括：用于DS-0，DS-1，CEPTn信号等的添加/删除应用的分插复用器装置; 一个SONET总线接口; 虚拟支路交叉连接模块，其跨越空间，时间和相位中的虚拟支路有效载荷，以产生新的基本上SONET格式的信号; 宽带交叉连接模块; DS-3 / SONET转换器; 和前端接口，包括DS3线路接口和各种STSn接口。 可以根据需要混合和匹配模块以适应多种应用。

公开(公告)号：US4598396A

公开(公告)日：1986-07-01

申请号：US596328

申请日：1984-04-03

申请人： Daniel C. Upp ,  William G. Bartholomay

发明人： Daniel C. Upp ,  William G. Bartholomay

IPC分类号： H03H7/48 ,  H04B3/03 ,  H04B3/54 ,  H04L5/14 ,  H04Q11/04 ,  H04B1/56 ,  H04B1/52 ,  H04J15/00

CPC分类号： H04B3/548 ,  H04L5/1423 ,  H04B2203/5425 ,  H04B2203/5437 ,  H04B2203/547

摘要： A duplex digital transmitter system is disclosed which permits simultaneous digital signal exchange over a two-wire loop. Two sets are provided at the ends of the loop, each having a three-port lattice adapted to separate the transmitted and received digital signals. The digital signals are encoded using a biphase scheme so that they have a zero D.C. component. Therefore the loop is used simultaneously to transmit D.C. power from one set to the other.

摘要翻译： 公开了一种双工数字发射机系统，其允许通过双线环路同时进行数字信号交换。 在环的两端提供两组，每组具有适于分离发送和接收的数字信号的三端口网格。 使用双相方案对数字信号进行编码，使得它们具有零D.C.分量。 因此，循环同时用于将直流功率从一组传输到另一组。

公开(公告)号：US4456991A

公开(公告)日：1984-06-26

申请号：US456638

申请日：1983-01-10

申请人： Ramon C. W. Chea, Jr. ,  Santanu Das ,  Daniel C. Upp ,  Jozef Cornu ,  Johan M. R. Danneels ,  Jean R. J. M. Taeymans

发明人： Ramon C. W. Chea, Jr. ,  Santanu Das ,  Daniel C. Upp ,  Jozef Cornu ,  Johan M. R. Danneels ,  Jean R. J. M. Taeymans

IPC分类号： H04Q11/04 ,  H04M3/00

CPC分类号： H04Q11/04

摘要： A telephone line circuit and system for interfacing digital exchange line circuits to a terminal interface of a switching network is disclosed. The system includes controllable active circuit impedance matching means for reducing impedance mismatch between a selected line circuit and the terminal interface. Control means controls both the active circuit impedance matching means for adjusting the effective circuit impedance to a value within a predetermined range, and the conditioning circuit gain pads for selectably adjusting the gain of a transmitted signal. Additionally, control means controls the d.c. line impedance and voltage for adjusting the effective line feed current to the subscriber loop, and provides interfaces for a plurality of line circuits to both a switching network and external processor. Supervision means provides supervision control signals to the control means and thereby permits the telephone line circuit system to provide desired telephone system functions.

摘要翻译： 公开了一种用于将数字交换线电路连接到交换网络的终端接口的电话线电路和系统。 该系统包括可控有源电路阻抗匹配装置，用于减少所选线路电路和终端接口之间的阻抗失配。 控制装置控制有源电路阻抗匹配装置，用于将有效电路阻抗调整到预定范围内的值，以及调节电路增益焊盘，用于可选择地调节发射信号的增益。 另外，控制装置控制直流。 线路阻抗和电压，用于调节到用户环路的有效馈电电流，并且向交换网络和外部处理器提供用于多条线路电路的接口。 监控装置向控制装置提供监控控制信号，从而允许电话线电路系统提供期望的电话系统功能。

公开(公告)号：US07349444B2

公开(公告)日：2008-03-25

申请号：US10924046

申请日：2004-08-23

申请人： Daniel C. Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Van Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

发明人： Daniel C. Upp ,  Suvhasis Mukhopadhyay ,  Bart Brosens ,  Kris Van Aken ,  Chitra Wadhwa ,  Sachin Mathur ,  Ramses Valvekens

IPC分类号： H04J3/06

CPC分类号： H04J3/0623

摘要： Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n×32 seconds (n×256,000 frames).

摘要翻译： 重新定时SONET信号的方法包括从STS-N信号中解复用STS-1信号，缓冲FIFO中的每个STS-1信号，确定随时间的FIFO深度，以及部分地基于FIFO深度确定指针泄漏率， 也基于接收到的指针移动速率。 根据当前优选的实施例，每个FIFO是29字节深。 如果FIFO深度为12-17字节，则不会发生泄漏。 如果深度为8-12字节或17-21字节，则设置缓慢的泄漏率。 如果深度为4-8字节或21-25字节，则设置快速泄漏率。 如果深度为0-4字节或25-29字节，则指针移动立即。 计算的泄漏率基于在nx32秒（nx256,000帧）的滑动窗口期间接收到的指针移动的净数（正和负移动相加的大小）。

公开(公告)号：US07333733B2

公开(公告)日：2008-02-19

申请号：US10383364

申请日：2003-03-07

申请人： Geoff W. Taylor ,  Rohinton Dehmubed ,  Daniel C. Upp

发明人： Geoff W. Taylor ,  Rohinton Dehmubed ,  Daniel C. Upp

IPC分类号： H04B10/00

CPC分类号： H01L29/66318 ,  H01L29/155 ,  H01L29/66462 ,  H01L29/802 ,  H03K3/42 ,  H03K17/79 ,  H03M1/667 ,  H03M1/74 ,  H03M1/808

摘要： An optoelectronic pulse generator is provided that includes a thyristor detector/emitter device having an input port and an output port. The thyristor detector/emitter device is adapted to detect an input optical pulse supplied to the input port and to produce an output optical pulse (via laser emission) and an output electrical pulse in response to the detected input optical pulse. The output optical pulse is output via the output port. An optical feedback path is operably coupled between the output port and the input port of the thyristor detector/emitter device. The optical feedback path supplies a portion of the output optical pulse produced by the thyristor detector/emitter device to the input port, thereby causing the thyristor detector/emitter device to produce a sequence of output optical pulses and a corresponding sequence of output electrical pulses. Preferably, the optical feedback path comprises a programmable optical delay line realized by a network of in-plane waveguide structures and directional coupler devices that are integrally formed with the thyristor device structure of the detector/emitter device.

摘要翻译： 提供了一种光电脉冲发生器，其包括具有输入端口和输出端口的晶闸管检测器/发射器装置。 晶闸管检测器/发射器件适于检测提供给输入端口的输入光脉冲并响应于检测到的输入光脉冲产生输出光脉冲（经由激光发射）和输出电脉冲。 输出光脉冲通过输出端口输出。 光学反馈路径可操作地耦合在输出端口和晶闸管检测器/发射器件的输入端口之间。 光学反馈路径将由晶闸管检测器/发射器件产生的输出光脉冲的一部分提供给输入端口，从而使晶闸管检测器/发射器件产生一系列输出光脉冲和相应的输出电脉冲序列。 优选地，光学反馈路径包括由面内波导结构的网络和与检测器/发射器件的晶闸管器件结构整体形成的定向耦合器件实现的可编程光学延迟线。

公开(公告)号：US06954473B2

公开(公告)日：2005-10-11

申请号：US10280892

申请日：2002-10-25

申请人： Rohinton Dehmubed ,  Geoff W. Taylor ,  Daniel C. Upp ,  Jianhong Cai

发明人： Rohinton Dehmubed ,  Geoff W. Taylor ,  Daniel C. Upp ,  Jianhong Cai

IPC分类号： H01L21/331 ,  H01L21/335 ,  H01L29/15 ,  H01L29/80 ,  H03K17/79 ,  H03M1/66 ,  H03M1/74 ,  H03M1/80 ,  H01S3/10

CPC分类号： H01L29/66318 ,  H01L29/155 ,  H01L29/66462 ,  H01L29/802 ,  H03K17/79 ,  H03M1/667 ,  H03M1/74 ,  H03M1/808

摘要： An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials. A plurality of such heterojunction thyristor based optoelectronic integrated circuits can be used to provide variable pulse delay over a plurality of channels. In addition, the heterojunction thyristor device is easily integrated with other optoelectronic devices formed from the same growth structure to form monolithic optoelectronic integrated circuits suitable for many diverse applications, including phased array communication systems.

摘要翻译： 光电集成电路包括形成在基板上的谐振腔。 异相结晶闸管器件形成在谐振腔中，用于检测输入光脉冲（或输入电脉冲），并响应于检测到的输入脉冲通过激光发射产生输出光脉冲。 异质结晶闸管器件包括耦合到电流源的沟道区，其从沟道区抽取电流。 输入脉冲和输出光脉冲之间的时间延迟可以通过配置电流源来从通道区域抽取恒定电流并调制输入脉冲的强度，或者通过改变从通道区域引出的电流量来改变电流 资源。 异质结晶闸管器件可以由III-V族材料的多层结构或者由应变硅材料的多层结构形成。 可以使用多个这样的异质结晶闸管的光电集成电路来在多个通道上提供可变的脉冲延迟。 此外，异质结晶闸管器件容易与由相同生长结构形成的其它光电器件集成，以形成适用于许多不同应用的单片光电集成电路，包括相控阵通信系统。

公开(公告)号：US06463111B1

公开(公告)日：2002-10-08

申请号：US09865324

申请日：2001-05-25

申请人： Daniel C. Upp

发明人： Daniel C. Upp

IPC分类号： H04L2500

CPC分类号： H04J3/076 ,  H03L7/06

摘要： The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference between the write and intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions, and a digitally controlled oscillator (DCO). The second FIFO has read and write counters, a phase-frequency detector, and an internal VCO controlled by length measurements of the second FIFO. The desynchronizer receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.

摘要翻译： 本发明的去同步器包括两个FIFO。 第一个FIFO具有两个地址计数器（写入和读取），一个中间计数寄存器，用于计算写入和中间计数与中间和读取计数之间的差异的电路，用于执行指针泄漏和其他算术功能的逻辑块，以及 数字控制振荡器（DCO）。 第二个FIFO具有读写计数器，一个相位检测器和一个由第二个FIFO的长度测量值控制的内部VCO。 去同步器从DS-3 / E3解映射器接收数据位，指针移动指示和填充指示，并使用第一个FIFO地址计数器等来除去低频分量，包括SONET / SDH系统间隙，以便 向具有高频相位调制的DS-3 / E3信号提供第二FIFO。 第二个FIFO消除了剩余的高频间隙抖动。

公开(公告)号：US5901146A

公开(公告)日：1999-05-04

申请号：US960499

申请日：1997-10-29

申请人： Daniel C. Upp

发明人： Daniel C. Upp

IPC分类号： G06F13/362 ,  H04L12/403 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/24

CPC分类号： H04L12/5601 ,  H04L12/403 ,  H04L12/4035 ,  H04Q11/0478 ,  H04L2012/5613 ,  H04L2012/5615 ,  H04L2012/5679

摘要： An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users. The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

公开(公告)号：US5608731A

公开(公告)日：1997-03-04

申请号：US414502

申请日：1995-03-31

申请人： Daniel C. Upp ,  Dan H. Wolaver

发明人： Daniel C. Upp ,  Dan H. Wolaver

IPC分类号： H04J3/06 ,  H04L12/56 ,  H04Q11/04 ,  H04L7/08

CPC分类号： H04J3/0632 ,  H04Q11/0478 ,  H04L2012/5652 ,  H04L2012/5674

摘要： An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

摘要翻译： 提供了一种SRTS时钟恢复装置和方法。 该装置广泛地包括可控目的地节点时钟发生器，例如数字可控振荡器，用于从目的地节点时钟和系统参考时钟产生本地RTS相关值的块，以及将进入的RTS相关值与 本地RTS相关值提供反馈误差或控制信号，用于调节可控时钟发生器。 如果需要，可以在循环中提供过滤误差信号的滤波器。 使用所提供的反馈回路，当目的地节点时钟比源时钟快时，误差信号将导致目的地节点时钟减慢，反之亦然。