公开(公告)号：US08023328B2

公开(公告)日：2011-09-20

申请号：US12338751

申请日：2008-12-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/10 ,  G11C16/3468

Abstract: A memory device is disclosed. The memory device includes a charge trapping layer, and a substrate underlying the charge trapping layer. The carriers are introduced into the charge trapping layer to make a first memory state, for example, when a positive voltage is applied to the gate. At least one of the carriers is released from the charge trapping layer to make a second memory state, for example, when a negative voltage is applied to the gate.

Abstract translation: 公开了一种存储器件。 存储器件包括电荷俘获层和电荷陷阱层下面的衬底。 载流子被引入电荷俘获层以形成第一存储器状态，例如当正电压施加到栅极时。 至少一个载体从电荷捕获层释放以形成第二存储器状态，例如当向栅极施加负电压时。

公开(公告)号：US07924626B2

公开(公告)日：2011-04-12

申请号：US12625438

申请日：2009-11-24

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04

CPC classification number: G11C16/16

Abstract: A method for operating a dielectric charge trapping memory cell as described herein includes applying an initial voltage from the gate to the substrate of the memory cell for a predetermined period of time to reduce the threshold voltage of the memory cell. The method includes applying a sequence of voltages from the gate to the substrate of the memory cell to further reduce the threshold voltage of the memory cell, wherein a subsequent voltage in the sequence of voltages has a lower magnitude from the gate to the substrate than that of a preceding voltage in the sequence of voltages.

Abstract translation: 用于操作如本文所述的介电电荷捕获存储器单元的方法包括将预定电压从栅极施加到存储器单元的衬底预定时间段以减小存储器单元的阈值电压。 该方法包括将来自栅极的电压序列施加到存储器单元的衬底，以进一步降低存储器单元的阈值电压，其中电压序列中的后续电压具有比栅极至衬底的量级小 的电压序列中的先前电压。

公开(公告)号：US07910981B2

公开(公告)日：2011-03-22

申请号：US11898528

申请日：2007-09-13

Applicant: Sheng-Chih Lai ,  Hang-Ting Lue

Inventor： Sheng-Chih Lai ,  Hang-Ting Lue

IPC: H01L29/792

CPC classification number: H01L29/517 ,  H01L29/513 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Abstract translation: 提供了具有非易失性存储器的半导体器件及其制造方法。 半导体器件包括基底材料和堆叠结构。 设置在基材上的堆叠结构至少包括隧穿层，捕获层和电介质层。 捕获层设置在隧道层上。 电介质层具有介电常数并且设置在捕获层上。 当电介质层进行处理时，电介质层从第一固态转变为第二固态。

公开(公告)号：US20110003452A1

公开(公告)日：2011-01-06

申请号：US12881570

申请日：2010-09-14

Applicant: SHENG CHIH LAI ,  Hang-Ting Lue ,  Chien Wei Liao

Inventor： SHENG CHIH LAI ,  Hang-Ting Lue ,  Chien Wei Liao

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L21/28282 ,  G11C8/10 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract translation: 阻挡介电工程的电荷捕获存储单元包括电荷俘获元件，其通过阻挡电介质与栅极分离，所述阻挡电介质包括与电荷俘获元件接触的缓冲层，例如可以以高质量制造的二氧化硅，以及 与栅极和沟道中的所述一个接触的第二覆盖层。 覆盖层的介电常数高于第一层的介电常数，优选包括高<！ - SIPO

公开(公告)号：US07838923B2

公开(公告)日：2010-11-23

申请号：US12102410

申请日：2008-04-14

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/792

CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/792

Abstract: A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.

Abstract translation: 描述了电荷捕获存储器单元，其具有沿通道侧面的凹槽注入并且具有与沟道相同的导电类型，并且哪些种植体的掺杂浓度高于通道的中心区域。 这样可以有效地禁止在通道侧的电荷俘获结构中由鸟嘴或其他异常引起的不均匀电荷捕获区域中的通道。 可以使用与标准浅沟槽隔离工艺兼容的工艺来形成口袋植入物。

公开(公告)号：US07772072B2

公开(公告)日：2010-08-10

申请号：US11845945

申请日：2007-08-28

Applicant: Szu-Yu Wang ,  Hang-Ting Lue

Inventor： Szu-Yu Wang ,  Hang-Ting Lue

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234

Abstract: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.

Abstract translation: 提供位于基板上的非易失性存储器。 非易失性存储器包括隧道层，电荷俘获复合层，栅极和源极/漏极区域。 隧道层位于衬底上，电荷捕获复合层位于隧道层上，栅极位于电荷捕获复合层上。 源极/漏极区位于隧道层两侧的衬底中。 通过电荷捕获复合层，非易失性存储器具有相对更好的编程和擦除性能以及更高的数据保留能力。 此外，由于不需要在电荷捕获复合层的形成中进行热处理，因此制造工艺的热预算低。

公开(公告)号：US20090114976A1

公开(公告)日：2009-05-07

申请号：US12338751

申请日：2008-12-18

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: H01L29/792

CPC classification number: G11C16/0466 ,  G11C16/10 ,  G11C16/3468

Abstract: A method for programming and erasing charge-trapping memory device is provided. The method includes applying a first negative voltage to a gate causing a dynamic balance state (RESET\ERASE state). Next, a positive voltage is applied to the gate to program the device. Then, a second negative voltage is applied to the gate to restore the device to the RESET\ERASE state.

Abstract translation: 提供了一种用于编程和擦除电荷俘获存储器件的方法。 该方法包括将第一负电压施加到导致动态平衡状态的门（RESET \ ERASE状态）。 接下来，向门施加正电压以对器件进行编程。 然后，第二个负电压被施加到门以将器件恢复到RESET \ ERASE状态。

公开(公告)号：US20090057752A1

公开(公告)日：2009-03-05

申请号：US11845945

申请日：2007-08-28

Applicant: Szu-Yu Wang ,  Hang-Ting Lue

Inventor： Szu-Yu Wang ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/4234

Abstract: A non-volatile memory located on a substrate is provided. The non-volatile memory includes a tunnel layer, a charge trapping composite layer, a gate and a source/drain region. The tunnel layer is located on the substrate, the charge trapping composite layer is located on the tunnel layer and the gate is located over the charge trapping composite layer. The source/drain region is located in the substrate on both sides of the tunnel layer. With the charge trapping composite layer, the non-volatile memory has relatively better programming and erasing performance and higher data retention ability. Furthermore, since there is no need to perform a thermal process in the formation of the charge trapping composite layer, thermal budget of the manufacturing process is low.

Abstract translation: 提供位于基板上的非易失性存储器。 非易失性存储器包括隧道层，电荷俘获复合层，栅极和源极/漏极区域。 隧道层位于衬底上，电荷捕获复合层位于隧道层上，栅极位于电荷捕获复合层上。 源极/漏极区位于隧道层两侧的衬底中。 通过电荷捕获复合层，非易失性存储器具有相对更好的编程和擦除性能以及更高的数据保留能力。 此外，由于不需要在电荷捕获复合层的形成中进行热处理，因此制造工艺的热预算低。

公开(公告)号：US20090039416A1

公开(公告)日：2009-02-12

申请号：US11845321

申请日：2007-08-27

Applicant: Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

Inventor： Sheng Chih Lai ,  Hang-Ting Lue ,  Chien Wei Liao

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/115 ,  G11C16/0466 ,  G11C16/0483 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/792

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract translation: 带隙设计的电荷捕获存储单元包括电荷捕获元件，其通过具有介电常数的金属掺杂氧化硅材料的阻挡层（例如掺铝氧化硅）与栅极分离，并与半导体本体分离，包括 通道由工程隧道电介质。

公开(公告)号：US07391652B2

公开(公告)日：2008-06-24

申请号：US11381760

申请日：2006-05-05

Applicant: Hang-Ting Lue

Inventor： Hang-Ting Lue

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/0466 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427

Abstract: A programming method for a p-channel memory cell, the memory cell includes a source, a drain and a gate. The gate is applies with a first voltage, which results in Fowler-Nordheim (−FN) hole injection, thereby causing the memory cell to be in a programmed state.

Abstract translation: 一种用于p沟道存储单元的编程方法，所述存储单元包括源极，漏极和栅极。 门施加第一电压，这导致Fowler-Nordheim（-FN）空穴注入，从而使存储器单元处于编程状态。