公开(公告)号：US09269583B1

公开(公告)日：2016-02-23

申请号：US14530082

申请日：2014-10-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Chih-Chieh Cheng ,  Wen-Jer Tsai

IPC: H01L21/8244 ,  H01L21/266 ,  H01L27/115 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L21/266 ,  H01L21/2253 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

Abstract: Provided is a method for fabricating a memory device, including the following steps. A plurality of semiconductor fin structures is formed on a substrate. Each semiconductor fin structure includes a first doped region and a body region on which the first doped region is disposed, and a trench is disposed between adjacent two semiconductor fin structures. A second doped region is formed in the substrate under the body regions of the semiconductor fin structures and the trenches. A plurality of first contacts are formed on the substrate. A plurality of second contacts are formed on the substrate. Each second contact is electrically connected with the corresponding first doped region.

Abstract translation: 提供一种用于制造存储器件的方法，包括以下步骤。 在基板上形成多个半导体翅片结构。 每个半导体鳍片结构包括第一掺杂区域和其上设置有第一掺杂区域的主体区域，并且在相邻的两个半导体鳍片结构之间设置沟槽。 第二掺杂区形成在半导体鳍结构体和沟槽的主体区域下方的衬底中。 在基板上形成多个第一触点。 在基板上形成多个第二触点。 每个第二接触件与相应的第一掺杂区域电连接。

公开(公告)号：US09209198B2

公开(公告)日：2015-12-08

申请号：US14275559

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.

Abstract translation: 提供了一种存储单元，其包括基板，第一导电类型的两个掺杂区域，第二导电类型的一个掺杂区域，两个堆叠结构和第一隔离结构。 第一导电类型的掺杂区域分别设置在基板中。 第二导电类型的掺杂区域设置在第一导电类型的两个掺杂区域之间的衬底中。 层叠结构设置在基板上并分别覆盖第一导电类型的对应掺杂区域和第二导电类型的掺杂区域的一部分。 每个堆叠结构包括一个电荷存储层。 第一隔离结构完全覆盖并与第一导电类型的每个掺杂区的底表面和第二导电类型的掺杂区的底表面接触。

公开(公告)号：US09048263B2

公开(公告)日：2015-06-02

申请号：US14314830

申请日：2014-06-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: H01L21/8247 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

Abstract: A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.

Abstract translation: 提供了一种非易失性存储器及其制造方法。 在该方法中，在基板上形成具有突出部的第一氧化物层。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和一对电荷存储间隔物上形成第二氧化物层。 导电层形成在第二氧化物层上，其中导电层完全位于一对电荷存储间隔物的顶部上。

公开(公告)号：US20140209992A1

公开(公告)日：2014-07-31

申请号：US13750606

申请日：2013-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11563 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.

Abstract translation: 提供一种用于制造包括以下步骤的非易失性存储器结构的制造方法。 在衬底中形成第一导电型掺杂层。 在基板上形成多个堆叠结构，并且每个堆叠结构都包括电荷存储结构。 在相邻的层叠结构之间的基板上形成第一电介质层。 在相邻的电荷存储结构之间的衬底中形成第二导电型掺杂区。 第二导电型掺杂区域与每个电荷存储结构具有重叠区域。 此外，第二导电型掺杂区域将第一导电类型掺杂层划分成彼此分离的多个第一导电型掺杂区域。 在第一电介质层上形成导电层。