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公开(公告)号：US20230402082A1
公开(公告)日：2023-12-14
申请号：US18235955
申请日：2023-08-21
IPC分类号： G11C11/22 , H01L29/788 , H01L29/423 , H01L29/78 , H01L29/66 , H10B51/30
CPC分类号： G11C11/223 , H01L29/788 , H01L29/42392 , H01L29/42324 , H01L29/42368 , H01L29/42376 , H01L29/78391 , H01L29/4234 , H01L29/6684 , H10B51/30 , H01L29/66825 , H01L29/7887 , H01L29/7889
摘要： A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
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公开(公告)号：US11769542B2
公开(公告)日：2023-09-26
申请号：US17501464
申请日：2021-10-14
IPC分类号： G11C11/22 , H01L29/788 , H01L29/423 , H01L29/78 , H01L29/66 , H10B51/30
CPC分类号： G11C11/223 , H01L29/4234 , H01L29/42324 , H01L29/42368 , H01L29/42376 , H01L29/42392 , H01L29/6684 , H01L29/66825 , H01L29/788 , H01L29/7887 , H01L29/7889 , H01L29/78391 , H10B51/30
摘要： A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.
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公开(公告)号：US11682736B2
公开(公告)日：2023-06-20
申请号：US17143815
申请日：2021-01-07
发明人： Yu-Chun Shen , Chi-Chung Jen , Ya-Chi Hung , Yu-Chu Lin , Wen-Chih Chiang
IPC分类号： H10B41/10 , H10B41/30 , H01L29/788 , H01L27/11519 , H01L29/66 , H01L29/423 , H01L21/28 , H01L27/11521
CPC分类号： H01L29/7887 , H01L27/11519 , H01L27/11521 , H01L29/40114 , H01L29/42328 , H01L29/66825
摘要： In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.
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公开(公告)号：US10074749B2
公开(公告)日：2018-09-11
申请号：US15095936
申请日：2016-04-11
发明人： Takamitsu Ishihara , Koichi Muraoka
IPC分类号： H01L29/423 , H01L29/788 , H01L21/28 , H01L29/792 , H01L27/11521 , H01L29/51
CPC分类号： H01L29/7887 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/512 , H01L29/7881 , H01L29/792
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.
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公开(公告)号：US10014308B2
公开(公告)日：2018-07-03
申请号：US15228236
申请日：2016-08-04
发明人： Stephane Zoll , Philippe Garnier
IPC分类号： H01L27/105 , H01L27/11539 , H01L29/788 , H01L21/28 , H01L27/11521
CPC分类号： H01L27/11539 , H01L27/11521 , H01L27/11536 , H01L29/40114 , H01L29/40117 , H01L29/42368 , H01L29/495 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.
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公开(公告)号：US09997640B2
公开(公告)日：2018-06-12
申请号：US15252250
申请日：2016-08-31
发明人： Zhijiong Luo
IPC分类号： H01L29/788 , H01L29/66 , G11C16/04 , G11C11/56 , H01L21/84 , H01L21/28 , H01L27/11521 , H01L27/12 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/7887 , G11C11/5621 , G11C16/0408 , H01L21/28273 , H01L21/84 , H01L27/11521 , H01L27/1203 , H01L27/1211 , H01L29/0847 , H01L29/1033 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/788 , H01L29/7881 , H01L29/7883
摘要： Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.
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公开(公告)号：US09911867B2
公开(公告)日：2018-03-06
申请号：US15200347
申请日：2016-07-01
IPC分类号： H01L29/788 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/7887 , H01L29/0653 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/7851
摘要： Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.
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公开(公告)号：US20180006158A1
公开(公告)日：2018-01-04
申请号：US15200347
申请日：2016-07-01
IPC分类号： H01L29/788 , H01L29/423 , H01L29/06 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7887 , H01L29/0653 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/7851
摘要： Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.
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9.发明申请Split Gate NAND Flash Memory Structure And Array, Method Of Programming, Erasing And Reading Thereof, And Method Of Manufacturing 有权分割门NAND闪存结构和阵列，编程，擦除和读取方法，以及制造方法公开(公告)号：US20170032846A1
公开(公告)日：2017-02-02
申请号：US15249306
申请日：2016-08-26
发明人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
CPC分类号： G11C16/0425 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3431 , G11C2216/18 , H01L21/28273 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L29/42328 , H01L29/66825 , H01L29/7887
摘要： A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
摘要翻译： 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。
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公开(公告)号：US20160372602A1
公开(公告)日：2016-12-22
申请号：US15252250
申请日：2016-08-31
发明人： Zhijiong Luo
IPC分类号： H01L29/788 , H01L29/78 , H01L27/12 , G11C16/04 , H01L29/66 , H01L29/10 , H01L29/08 , H01L27/115 , H01L21/28
CPC分类号： H01L29/7887 , G11C11/5621 , G11C16/0408 , H01L21/28273 , H01L21/84 , H01L27/11521 , H01L27/1203 , H01L27/1211 , H01L29/0847 , H01L29/1033 , H01L29/66795 , H01L29/66825 , H01L29/785 , H01L29/788 , H01L29/7881 , H01L29/7883
摘要： Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.
摘要翻译： 技术通常被描述为涉及双通道存储器件，系统和制造方法。 各种描述的器件包括通过形成在半导体器件的双栅极结构下方的衬底来利用前通道和后通道。 在栅极结构的相对侧上使用两对触点，其中接触对形成在半导体器件的不同掺杂层上，可以将多个位存储在用作单个存储器单元的半导体器件中。 存储可以通过在浮动栅极上存储不同数量或类型的电荷来实现，其中电荷可能影响器件的通道的导通状态。 通过检测通道的导通状态，例如开路，闭路或高电阻，低电阻，可以检测存储在设备上的数据（“0”或“1”）。
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