公开(公告)号：US20220222180A1

公开(公告)日：2022-07-14

申请号：US17657922

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US20220114093A1

公开(公告)日：2022-04-14

申请号：US17070774

申请日：2020-10-14

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/02 ,  G06F12/0802

Abstract: Described apparatuses and methods balance memory-portion accessing. Some memory architectures are designed to accelerate memory accesses using schemes that may be at least partially dependent on memory access requests being distributed roughly equally across multiple memory portions of a memory. Examples of such memory portions include cache sets of cache memories and memory banks of multibank memories. Some code, however, may execute in a manner that concentrates memory accesses in a subset of the total memory portions, which can reduce memory responsiveness in these memory types. To account for such behaviors, described techniques can shuffle memory addresses based on a shuffle map to produce shuffled memory addresses. The shuffle map can be determined based on a count of the occurrences of a reference bit value at bit positions of the memory addresses. Using the shuffled memory address for memory requests can substantially balance the accesses across the memory portions.

公开(公告)号：US11294808B2

公开(公告)日：2022-04-05

申请号：US16880248

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0804 ,  G06F12/0864

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.

公开(公告)号：US11151043B2

公开(公告)日：2021-10-19

申请号：US16538551

申请日：2019-08-12

Applicant: Micron Technology, inc.

Inventor： David Andrew Roberts

IPC: G06F12/0862 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for predictive memory access are described. Memory control circuitry instructs a memory array to read a data block from or write the data block to a location targeted by a memory access request, determines memory access information including a data value correlation parameter determined based on data bits used to indicate a raw data value in the data block and/or an inter-demand delay correlation parameter determined based on a demand time of the memory access request, predicts that read access to another location in the memory array will subsequently be demanded by another memory access request based on the data value correlation parameter and/or the inter-demand delay correlation parameter, and instructs the memory array to output another data block stored at the other location to a different memory level that provides faster data access speed before the other memory access request is received.

公开(公告)号：US20250117154A1

公开(公告)日：2025-04-10

申请号：US18982470

申请日：2024-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： David Andrew Roberts

IPC: G06F3/06

Abstract: A host system includes a memory and a processing device coupled to the memory to perform operations including obtaining log data from a memory sub-system of a plurality of memory sub-systems, wherein the log data reflects memory usage of a memory device of the memory sub-system, wherein the memory device is shared by the plurality of host systems, including the host system, connected to the plurality of memory sub-systems; and determining, based on the log data, a schedule of a plurality of processes running on the plurality of host systems, wherein the plurality of processes share the memory device.

公开(公告)号：US20250077125A1

公开(公告)日：2025-03-06

申请号：US18948302

申请日：2024-11-14

Applicant: Micron Technology, Inc.

Inventor： Nabeel Meeramohideen Mohamed ,  Steven Andrew Moyer ,  David Andrew Roberts

IPC: G06F3/06

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

公开(公告)号：US20250036284A1

公开(公告)日：2025-01-30

申请号：US18774784

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Patrick Estep

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for data transfer between tiered memory devices are described. A memory system may include a data transfer engine to manage data transfers between different tiers of memory devices within the memory system. The data transfer engine may receive a command which includes a set of source addresses of each of a set of data sets and a set of destination addresses to which the data sets are to be transferred. The data transfer engine may schedule and perform a transfer operation to transfer each of the set of data sets from the respective source address to the respective destination address. The command may further include an indication of an interrupt policy of a set of interrupt policies supported by the data transfer engine. The set of interrupt policies may determine how the data transfer engine may handle interruptions to the data transfer operation.

公开(公告)号：US20240427701A1

公开(公告)日：2024-12-26

申请号：US18760848

申请日：2024-07-01

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F12/0815

Abstract: An access counter associated with a segment of a memory device is maintained. The segment comprises a plurality of lines. A first count of the plurality of lines is identified. A subset of the plurality of lines of the segment is monitored. A second count of the subset of the plurality of lines is identified. An access notification for a first line of the subset of the plurality of lines is received. A first value of the access counter is changed by a second value. The second value is weighted based on the first count and the second count. Based on the first value of the access counter, a memory management scheme is implemented.

公开(公告)号：US20240311084A1

公开(公告)日：2024-09-19

申请号：US18606809

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Tony M. Brewer ,  Scott Lynn Michaelis

IPC: G06F7/58

CPC classification number: G06F7/582

Abstract: Various examples are directed to systems and methods for generating a set of pseudorandom numbers in a computing system comprising a compute element and a memory device. A memory controller of the memory device may receive, from the compute element, an indication to generate a set of pseudorandom numbers. The memory controller may generate the set of pseudorandom numbers and write the set of pseudorandom numbers to a memory array of the memory device for access by the compute element.

公开(公告)号：US20240281331A1

公开(公告)日：2024-08-22

申请号：US18581842

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts

IPC: G06F11/14 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F11/1407 ,  G06F9/455 ,  G06F9/5016 ,  G06F11/1438 ,  G06F2209/5011

Abstract: Disclosed in some examples, are methods, systems, and machine-readable mediums in which application state is saved using in-memory versioning in a shared memory pool of disaggregated memory. By utilizing a disaggregated memory pool, the processing resources may be on separate devices than the memory those resources are using. As a result of this architecture, a failure of hardware of processing resources or an application does not necessarily also cause the hardware resources of the memory devices to fail. This allows a standby application executing on standby processing resources to quickly resume execution when a primary application fails by utilizing the memory pool assigned to the primary application in the memory pool.