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    WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CROSS CORRELATING WIRELESS TRANSMISSIONS
    22.
    发明申请
    WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CROSS CORRELATING WIRELESS TRANSMISSIONS 审中-公开

    公开(公告)号：US20180167194A1

    公开(公告)日：2018-06-14

    申请号：US15374831

    申请日：2016-12-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: H04L7/04 ,  H04L27/26

    CPC classification number: H04L7/042 ,  H04L27/0006 ,  H04L27/2647 ,  H04L27/2663 ,  H04L27/2678

    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (RF) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. The electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. A decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. Examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.

    SYSTEM ON A CHIP WITH DEEP LEARNING ACCELERATOR AND RANDOM ACCESS MEMORY
    23.
    发明申请
    SYSTEM ON A CHIP WITH DEEP LEARNING ACCELERATOR AND RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20250117659A1

    公开(公告)日：2025-04-10

    申请号：US18984365

    申请日：2024-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Poorna Kale ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N5/04

    Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. An integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or connections among the random access memory, the deep learning accelerator and the central processing unit; and an input/output interface to an external peripheral bus. While the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.

    COMPUTATIONAL STORAGE AND NETWORKED BASED SYSTEM
    24.
    发明申请
    COMPUTATIONAL STORAGE AND NETWORKED BASED SYSTEM 有权

    公开(公告)号：US20250053342A1

    公开(公告)日：2025-02-13

    申请号：US18927374

    申请日：2024-10-25

    Applicant: Micron Technology, Inc.

    Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

    Computational storage and networked based system
    26.
    发明授权
    Computational storage and networked based system 有权

    公开(公告)号：US12175130B2

    公开(公告)日：2024-12-24

    申请号：US18152063

    申请日：2023-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Shanyuan Gao ,  Sen Ma ,  Moon Mark Hur ,  Jaime Cummins

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

    AGGREGATE INTERFERENCE CANCELATION USING NEURAL NETWORKS
    27.
    发明公开
    AGGREGATE INTERFERENCE CANCELATION USING NEURAL NETWORKS 审中-公开

    公开(公告)号：US20240291511A1

    公开(公告)日：2024-08-29

    申请号：US18584739

    申请日：2024-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: H04B1/10 ,  H04B17/345 ,  H04B17/391

    CPC classification number: H04B1/1036 ,  H04B17/345 ,  H04B17/3913

    Abstract: A wireless device includes a wireless receiver configured to receive a respective plurality of receive signals from a respective receiving antenna of a plurality of receiving antennas and an interference mitigation circuit coupled to the respective receiving antenna and including a neural network. The interference mitigation circuit is configured to receive an interference mitigation mode signal indicating two or more interference types of a plurality of interference types to mitigate. In response to the interference mitigation mode signal, the interference mitigation circuit is configured to adjust weights applied by the neural network for adjusted signals to cause the neural network to mitigate the two or more interference types of the plurality of interference types while receiving the plurality of receive signals.

    WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CROSS CORRELATING WIRELESS TRANSMISSIONS
    28.
    发明公开
    WIRELESS DEVICES AND SYSTEMS INCLUDING EXAMPLES OF CROSS CORRELATING WIRELESS TRANSMISSIONS 审中-公开

    公开(公告)号：US20240178987A1

    公开(公告)日：2024-05-30

    申请号：US18436965

    申请日：2024-02-08

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: H04L7/04 ,  H04L27/00 ,  H04L27/26

    CPC classification number: H04L7/042 ,  H04L27/0006 ,  H04L27/2647 ,  H04L27/2663 ,  H04L27/2678

    Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of cross correlation including symbols indicative of radio frequency (RF) energy. An electronic device including a statistic calculator may be configured to calculate a statistic including the cross-correlation of the symbols. The electronic device may include a comparator configured to provide a signal indicative of a presence or absence of a wireless communication signal in the particular portion of the wireless spectrum based on a comparison of the statistic with a threshold. A decoder/precoder may be configured to receive the signal indicative of the presence or absence of the wireless communication signal and to decode the symbols responsive to a signal indicative of the presence of the wireless communication signal. Examples of systems and methods described herein may facilitate the processing of data for wireless communications in a power-efficient and time-efficient manner.

    TENSOR MEMORY ACCESS BASED IMPLEMENTATION FOR MASSIVE AND ULTRA-MASSIVE MIMO SYSTEMS
    29.
    发明公开
    TENSOR MEMORY ACCESS BASED IMPLEMENTATION FOR MASSIVE AND ULTRA-MASSIVE MIMO SYSTEMS 审中-公开

    公开(公告)号：US20240078040A1

    公开(公告)日：2024-03-07

    申请号：US17929954

    申请日：2022-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0622 ,  G06F3/0656 ,  G06F3/067

    Abstract: Examples described herein include systems and methods which include a multiple input, multiple output transceiver including a plurality of receive antenna configured to receive a plurality of receive signals, and a wireless receiver coupled to the plurality of antenna and configured to receive and decode the plurality of receive signals. The transceiver includes a memory array and a memory controller. The memory controller includes a data address generator configured to, during the decode of the plurality of receive signals, generate at least one memory address according to an access mode of a memory command associated with a memory access operation. The at least one memory address corresponds to a specific sequence of memory access instructions to access a memory cell of the memory array.

    Neuron calculator for artificial neural networks
    30.
    发明授权
    Neuron calculator for artificial neural networks 有权

    公开(公告)号：US11870513B2

    公开(公告)日：2024-01-09

    申请号：US17362672

    申请日：2021-06-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC: G06K9/00 ,  H04B7/0413 ,  G06N3/08 ,  G06N3/04

    CPC classification number: H04B7/0413 ,  G06N3/04 ,  G06N3/08

    Abstract: Examples described herein include systems and methods, including wireless devices and systems with neuron calculators that may perform one or more functionalities of a wireless transceiver. The neuron calculator calculates output signals that may be implemented, for example, using accumulation units that sum the multiplicative processing results of ordered sets from ordered neurons with connection weights for each connection between an ordered neuron and outputs of the neuron calculator. The ordered sets may be a combination of some input signals, with the number of signals determined by an order of the neuron. Accordingly, a kth-order neuron may include an ordered set comprising product values of k input signals, where the input signals are selected from a set of k-combinations with repetition. As an example in a wireless transceiver, the neuron calculator may perform channel estimation as a channel estimation processing component of the receiver portion of a wireless transceiver.

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