公开(公告)号：US10373654B1

公开(公告)日：2019-08-06

申请号：US15976737

申请日：2018-05-10

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Liang Chen

IPC: G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L25/065

Abstract: A memory device includes a first die configured to: generate a segment set based on a source data, wherein: the source data is information corresponding to a device operation, the source data having a block length representing a number of bits therein, the segment set including at least a first segment and a second segment, the first segment and the second segment having a number of bits less than the block length, and communicate the segment set with the second die; a second die configured to process the segment set according to the device operation; and a set of inter-die connectors electrically coupling the first die and the second die, the inter-die connectors include a number of dedicated Through-Silicon-Vias (TSVs), wherein the number is less than the block length.

公开(公告)号：US11456031B2

公开(公告)日：2022-09-27

申请号：US17116634

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Liang Chen

IPC: G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A host device and memory device perform internal write leveling of a data strobe with a write command. The memory device includes an input-output interface that receives the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal. The internal write circuitry includes an emulation loop configured to emulate circuitry in a clock path of a write clock generated from the clock and used to generate a feedback clock. The internal write circuitry includes a write delay lock loop configured to receive the write clock and the feedback clock to determine a number of cycles used for the loop, transmit the number of cycles to the host device to be used as a cycle adjust in an internal write leveling process, and complete the internal write leveling process with the host device using the cycle adjust.

公开(公告)号：US20190259442A1

公开(公告)日：2019-08-22

申请号：US15955330

申请日：2018-04-17

Applicant: Micron Technology, Inc.

Inventor： Liang Chen ,  Ming-Bo Liu

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.

公开(公告)号：US20190259433A1

公开(公告)日：2019-08-22

申请号：US16051202

申请日：2018-07-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen ,  David R. Brown

IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C8/18 ,  G11C8/10

Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.

公开(公告)号：US20190235760A1

公开(公告)日：2019-08-01

申请号：US15883956

申请日：2018-01-30

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Liang Chen ,  Daniel B. Penney

IPC: G06F3/06

Abstract: Techniques provided herein compensate for an internal and external timing skew between a data strobe (DQS) and a clock (CLK), by: executing at least one write leveling initialization procedure (WLInit) that uses a mode-register-write (MRW) command to synchronize a timing between a data strobe (DQS) with a clock (CLK) based upon capture of an internal write command. Internal and external timing skew is identified based upon the WLInit. The internal timing skew is skew caused internal to a memory device and the external timing skew is skew caused external to the memory device. A timing between the DQS and the CLK is adjusted based upon the internal and external timing skew.