公开(公告)号：US10580463B2

公开(公告)日：2020-03-03

申请号：US16380912

申请日：2019-04-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mamoru Nishizaki

IPC: G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  G11C7/12 ,  G11C7/10 ,  H01L23/522 ,  G11C7/06 ,  G11C7/04 ,  G11C7/18 ,  G11C8/14 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

公开(公告)号：US20190057726A1

公开(公告)日：2019-02-21

申请号：US15709250

申请日：2017-09-19

Applicant: Micron Technology, Inc.

Inventor： Mamoru Nishizaki

IPC: G11C5/06 ,  H01L23/528 ,  G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  H01L23/522 ,  G11C7/12

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

公开(公告)号：US09142629B2

公开(公告)日：2015-09-22

申请号：US14447976

申请日：2014-07-31

Applicant: Micron Technology, Inc.

Inventor： Mamoru Nishizaki

IPC: H01L27/02 ,  H01L29/423 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/42376 ,  G06F1/3287 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/7817 ,  Y02D10/171

Abstract: A device includes a first transistor including a first gate electrode including first and second parallel electrode portions each extending in a first direction, and a first connecting electrode portion extending in a second direction approximately orthogonal to the first direction and connecting one ends of the first and second parallel electrode portions to each other, and first and second diffusion layers separated from each other by a channel region under the first gate electrode, a first output line connected to the first diffusion layer of the first transistor, and a second transistor comprising a second gate electrode extending in the second direction, and the second transistor being configured to use the second diffusion layer of the first transistor as one of two diffusion layers that are separated from each other by a channel region under the second gate electrode.

Abstract translation: 一种器件包括：第一晶体管，包括第一栅电极，第一栅电极包括分别沿第一方向延伸的第一和第二平行电极部分;以及第一连接电极部分，其沿大致正交于第一方向的第二方向延伸，并且连接第一和 第二平行电极部分彼此分开，并且第一和第二扩散层通过第一栅电极下方的沟道区彼此分离，第一输出线连接到第一晶体管的第一扩散层，第二晶体管包括第二 栅电极沿第二方向延伸，第二晶体管被配置为将第一晶体管的第二扩散层用作通过第二栅电极下方的沟道区彼此分离的两个扩散层之一。