公开(公告)号：US11480514B2

公开(公告)日：2022-10-25

申请号：US16424415

申请日：2019-05-28

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： G01N15/14 ,  G01N21/64

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR, FLIM and flow cytometry applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. The picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US10911171B2

公开(公告)日：2021-02-02

申请号：US16265322

申请日：2019-02-01

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： H04J3/06 ,  H03K5/135 ,  H03K5/133 ,  H04L7/00

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US08423814B2

公开(公告)日：2013-04-16

申请号：US12728101

申请日：2010-03-19

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： G06F1/00 ,  G06F5/06 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F1/08

摘要： Embodiments of the invention relate to programmable data register circuits and programmable clock generation circuits For example, some embodiments include a buffer circuit for receiving input data and sending output data signals along a series of signal lines with a signal strength, and a signal modulator configured to determine the signal strength based on a control input. Some embodiments include a clock generation circuit for receiving clock reference and sending output clock signals along a series of signal lines with a signal character, and a signal modulator configured to determine the signal character based on a control input.

摘要翻译： 本发明的实施例涉及可编程数据寄存器电路和可编程时钟生成电路。例如，一些实施例包括用于接收输入数据并沿着具有信号强度的一系列信号线发送输出数据信号的缓冲电路，以及配置为 根据控制输入确定信号强度。 一些实施例包括用于接收时钟参考并且沿着一系列具有信号字符的信号线发送输出时钟信号的时钟产生电路，以及被配置为基于控制输入来确定信号字符的信号调制器。

公开(公告)号：US08000412B1

公开(公告)日：2011-08-16

申请号：US11756139

申请日：2007-05-31

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： H03K5/159

CPC分类号： H04L25/4904 ,  H04L25/0272

摘要： The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.

摘要翻译： 本发明涉及采用差分归零信令的低功率串行链路。 与一些实施例一致的接收机电路包括用于接收形成差分归零信令的差分串行数据信号的输入电路和时钟恢复电路。 时钟恢复电路耦合到输入电路，并且包括被配置为通过使用所述差分串行数据信号产生时钟信号的逻辑门。

公开(公告)号：US20080260071A1

公开(公告)日：2008-10-23

申请号：US12130732

申请日：2008-05-30

申请人： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

发明人： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Sekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC分类号： H03D3/24 ,  H03B21/00

CPC分类号： H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。