公开(公告)号：US12021536B2

公开(公告)日：2024-06-25

申请号：US17942077

申请日：2022-09-09

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： H03L7/06 ,  G01N15/14 ,  G01N15/1429 ,  G01S7/4865 ,  G01S17/26 ,  G01S17/88 ,  G01T1/29 ,  A61B6/00 ,  G01N15/10

CPC分类号： H03L7/06 ,  G01N15/1429 ,  G01N15/1459 ,  G01S7/4865 ,  G01S17/26 ,  G01S17/88 ,  G01T1/2985 ,  A61B6/4417 ,  G01N2015/1006

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US20190305865A1

公开(公告)日：2019-10-03

申请号：US16265322

申请日：2019-02-01

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： H04J3/06 ,  H03K5/135 ,  H03K5/133 ,  H04L7/00

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.

公开(公告)号：US08964905B1

公开(公告)日：2015-02-24

申请号：US13173576

申请日：2011-06-30

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： H03K5/159

CPC分类号： H04L25/4904 ,  H04L25/0272

摘要： The present invention relates to a low power serial link employing differential return-to-zero signaling. A receiver circuit consistent with some embodiments includes an input circuit for receiving differential serial data signals that form a differential return-to-zero signaling and a clock recovery circuit. The clock recovery circuit is coupled to the input circuit and includes a logic gate configured to generate a clock signal by using said differential serial data signals.

摘要翻译： 本发明涉及采用差分归零信令的低功率串行链路。 与一些实施例一致的接收机电路包括用于接收形成差分归零信令的差分串行数据信号的输入电路和时钟恢复电路。 时钟恢复电路耦合到输入电路，并且包括被配置为通过使用所述差分串行数据信号产生时钟信号的逻辑门。

公开(公告)号：US07679345B1

公开(公告)日：2010-03-16

申请号：US11869595

申请日：2007-10-09

申请人： Shwetabh Verma ,  Marc Loinaz

发明人： Shwetabh Verma ,  Marc Loinaz

IPC分类号： G05F1/40

CPC分类号： G05F1/575

摘要： A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

摘要翻译： 数字线性稳压器包括比较器，有限状态机和当前的数模转换器（DAC）。 优选地，比较器被耦合以接收提供给动态负载的参考电压和工作电压。 比较器根据参考电压和工作电压之间的比较，在时钟周期内产生二进制输出。 有限状态机（FSM）被耦合以接收指示数字线性电压调节器的目标操作状态的至少一个控制信号。 FSM从比较器接收二进制输出，并在时钟周期内根据数字线性稳压器的目标工作状态和二进制输出产生数字字。 当前的DAC耦合到FSM，接收数字字，并将电流以期望的电压传递给动态负载。

公开(公告)号：US20190302245A1

公开(公告)日：2019-10-03

申请号：US16265364

申请日：2019-02-01

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： G01S7/486 ,  G01S7/481 ,  G01S17/88

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips

公开(公告)号：US08520744B2

公开(公告)日：2013-08-27

申请号：US12728113

申请日：2010-03-19

申请人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

发明人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

IPC分类号： H04B3/00

CPC分类号： H03L5/00 ,  G01R31/2851 ,  G06F7/00 ,  G06F21/00 ,  H03K19/0002

摘要： Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

摘要翻译： 方法和电路为受限制的一组通信线路上的多功能电路提供功能适当的信号。 第一通信线路接收数字信号。 第二通信线路用于与第一功能有关的数字信号。 在另外的步骤中，该方法包括基于第一通信线路上的多值逻辑数字信号启动产生二次功能激活信号的激活过程。 在接收到第二功能激活信号时，第二通信线路用于与第二功能相关的数字信号。 优选的激活过程包括监视用于数字签名的第二通信线路，并且在检测到适当的签名时发送激活信号。

公开(公告)号：US20110228860A1

公开(公告)日：2011-09-22

申请号：US12728113

申请日：2010-03-19

申请人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

发明人： Marc Loinaz ,  Stefanos Sidiropoulos ,  Whay Sing Lee

IPC分类号： H04B3/00

CPC分类号： H03L5/00 ,  G01R31/2851 ,  G06F7/00 ,  G06F21/00 ,  H03K19/0002

摘要： Methods and circuits provide function-appropriate signaling to multi-functional circuits on a constrained set of communication lines. A first communication line receives digital signals. The second communication line is employed for digital signaling related to a first function. In further steps, the method comprises initiating, based on a multi-value logic digital signal on the first communication line, an activation process that generates a second-function activation signal. Upon receipt of the second-function activation signal, the second communication line is employed for digital signaling related to a second function. Preferred activation processes involve monitoring the second communication line for a digital signature and sending the activation signal upon detection of an appropriate signature.

摘要翻译： 方法和电路为受限制的一组通信线路上的多功能电路提供功能适当的信令。 第一通信线路接收数字信号。 第二通信线路用于与第一功能有关的数字信号。 在另外的步骤中，该方法包括基于第一通信线路上的多值逻辑数字信号启动产生二次功能激活信号的激活过程。 在接收到第二功能激活信号时，第二通信线路用于与第二功能相关的数字信号。 优选的激活过程包括监视用于数字签名的第二通信线路，并且在检测到适当的签名时发送激活信号。

公开(公告)号：US20100164445A1

公开(公告)日：2010-07-01

申请号：US12723538

申请日：2010-03-12

申请人： Shwetabh Verma ,  Marc Loinaz

发明人： Shwetabh Verma ,  Marc Loinaz

IPC分类号： G05F1/10

CPC分类号： G05F1/575

摘要： A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator generates, during a clock cycle, a binary output based on a comparison between reference and operating voltages. The finite state machine (FSM) is coupled to receive at least one control signal that indicates a target operating state for the digital linear voltage regulator. The FSM receives the binary output from the comparator and generates a digital word, during a clock cycle, based on the target operating state of the digital linear voltage regulator and on the binary output. The current DAC is coupled to the FSM, receives the digital word and delivers current at the desired voltage to the dynamic load.

摘要翻译： 数字线性稳压器包括比较器，有限状态机和当前的数模转换器（DAC）。 优选地，比较器被耦合以接收提供给动态负载的参考电压和工作电压。 比较器根据参考电压和工作电压之间的比较，在时钟周期内产生二进制输出。 有限状态机（FSM）被耦合以接收指示数字线性电压调节器的目标操作状态的至少一个控制信号。 FSM从比较器接收二进制输出，并在时钟周期内根据数字线性稳压器的目标工作状态和二进制输出产生数字字。 当前的DAC耦合到FSM，接收数字字，并将电流以期望的电压传递给动态负载。

公开(公告)号：US07436229B2

公开(公告)日：2008-10-14

申请号：US11861690

申请日：2007-09-26

申请人： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

发明人： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC分类号： H03L7/06

CPC分类号： H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

摘要： A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

摘要翻译： 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US12081223B2

公开(公告)日：2024-09-03

申请号：US16265400

申请日：2019-02-01

申请人： Marc Loinaz

发明人： Marc Loinaz

IPC分类号： G01P3/36 ,  G01N15/14 ,  G01N15/1429 ,  G01S7/4865 ,  G01S17/26 ,  G01S17/88 ,  G01T1/29 ,  H03L7/06 ,  A61B6/00 ,  G01N15/10

CPC分类号： H03L7/06 ,  G01N15/1429 ,  G01N15/1459 ,  G01S7/4865 ,  G01S17/26 ,  G01S17/88 ,  G01T1/2985 ,  A61B6/4417 ,  G01N2015/1006

摘要： A sensor network, which includes a sensor controller serially coupled to a plurality of sensor modules, is configured to program the sensor modules so as to transfer measurement data to the sensor controller and to synchronize the sensor modules to picosecond accuracy via on-chip or on-module custom circuits and a physical layer protocol. The sensor network has applications for use in PET, LiDAR or FLIM applications. Synchronization, within picosecond accuracy, is achieved through use of a picosecond time digitization circuit. Specifically, the picosecond time digitization circuit is used to measure on-chip delays with high accuracy and precision. The delay measurements are directly comparable between separate chips even with voltage and temperature variations between chips.