公开(公告)号：US07937560B2

公开(公告)日：2011-05-03

申请号：US12121292

申请日：2008-05-15

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F15/76 ,  G06F1/00

CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

公开(公告)号：US07895459B2

公开(公告)日：2011-02-22

申请号：US11938899

申请日：2007-11-13

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

摘要翻译： 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，根据历史日志预测后续功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

公开(公告)号：US20110019819A1

公开(公告)日：2011-01-27

申请号：US12507481

申请日：2009-07-22

申请人： Kerry Bernstein ,  Sebastian T. Ventrone

发明人： Kerry Bernstein ,  Sebastian T. Ventrone

IPC分类号： H04K1/02

CPC分类号： H04K3/825 ,  H04K3/42

摘要： A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.

摘要翻译： 提供了用于保护驻留在电路（例如，处理器）上的信息的系统。 特别地，提供了一种用于屏蔽使用随机噪声发生器与低噪声放大器和天线组合的从电路发射的电磁干扰（EMI）发射的系统和方法。 随机数发生器匹配要保护的电路的频率，并产生要叠加在数据上的随机信号。 低噪声放大器从随机数发生器接收随机信号，并且天线从低噪声放大器接收随机信号，并发送随机信号以掩蔽要被保护的电路的数据。

公开(公告)号：US07865862B2

公开(公告)日：2011-01-04

申请号：US11937106

申请日：2007-11-08

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F9/3836 ,  G06F9/3885

摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令 执行单位 以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令 ，基于指令的吞吐量性能。

公开(公告)号：US07791968B2

公开(公告)日：2010-09-07

申请号：US11924955

申请日：2007-10-26

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/56 ,  G11C2029/0403 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device.

摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）装置; 以及耦合到所述PD SOI器件的测量装置，用于测量所述PD SOI器件的表示其体电压的状态，所述测量装置通信地耦合到计算装置，所述计算装置基于所述计算装置确定所述数据保持装置中的数据的历史状态 测量PD SOI器件的状态。

公开(公告)号：US07755420B2

公开(公告)日：2010-07-13

申请号：US12196718

申请日：2008-08-22

申请人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

发明人： Anthony R. Bonaccio ,  Hayden C. Cranford, Jr. ,  Joseph A. Iadanza ,  Sebastian T. Ventrone ,  Stephen D. Wyatt

IPC分类号： H03K5/00

CPC分类号： G05F1/46

摘要： Analog supply for an analog circuit and process for supplying an analog signal to an analog circuit. The analog supply includes a noise filter having a variable resistor, and a control device coupled to adjust the variable resistor. The control device is structured and arranged to set the resistance of the variable resistor to maximize noise filtering and optimize performance of the analog circuit.

摘要翻译： 用于模拟电路的模拟电源和用于向模拟电路提供模拟信号的过程。 模拟电源包括具有可变电阻器的噪声滤波器和耦合以调节可变电阻器的控制装置。 控制装置被构造和布置成设置可变电阻器的电阻以最大化噪声滤波并优化模拟电路的性能。

公开(公告)号：US20100031067A1

公开(公告)日：2010-02-04

申请号：US12183099

申请日：2008-07-31

申请人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

发明人： Igor Arsovski ,  Hayden C. Cranford, JR. ,  Sebastian T. Ventrone

IPC分类号： G06F1/03

CPC分类号： G06F1/03 ,  G06F1/26

摘要： A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element, the storage location including an anti-noise response signature, and utilizing the anti-noise response signature to proactively generate an anti-noise response in a power supply network in at least a portion of the integrated circuit at about the time of execution of the first IC event sequence. Anti-noise response signatures may be adaptively updated and/or created based on noise measurements made corresponding to execution of an IC event sequence by the integrated circuit.

摘要翻译： 一种用于集成电路的电源网络的主动噪声抑制系统和方法。 该系统和方法包括：向存储元件接收IC事件序列，将IC事件序列与第二存储器元件中的存储位置相关联，存储位置包括抗噪声响应签名，并将抗噪声响应签名 在执行第一IC事件序列时，在集成电路的至少一部分中，主动地在电力供应网络中产生抗噪声响应。 基于通过集成电路执行IC事件序列进行的噪声测量可以自适应地更新和/或创建抗噪声响应签名。

公开(公告)号：US20090254781A1

公开(公告)日：2009-10-08

申请号：US12479914

申请日：2009-06-08

申请人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

发明人： Anthony R. Bonaccio ,  Michael LeStrange ,  William R. Tonti ,  Sebastian T. Ventrone

IPC分类号： G06F11/07

CPC分类号： G06F1/04

摘要： A circuit for preventing failure in an integrated circuit. The circuit including: an original circuit; one or more redundant circuits; and a repair processor, including a clock cycle counter configured to count pulses of a pulsed signal, the repair processor configured to (a) replace the original circuit with a first redundant circuit or (b) configured to select another redundant circuit, the selection in sequence from a second redundant circuit to a last redundant circuit, and to replace a previously selected redundant circuit with the selected redundant circuit each time the cycle counter reaches a predetermined count of a set of pre-determined cycle counts.

摘要翻译： 一种用于防止集成电路故障的电路。 电路包括：原电路; 一个或多个冗余电路; 以及修复处理器，包括被配置为对脉冲信号的脉冲进行计数的时钟周期计数器，所述修复处理器被配置为（a）用第一冗余电路替换所述原始电路，或者（b）被配置为选择另一冗余电路， 从第二冗余电路到最后一个冗余电路的序列，并且每当循环计数器达到一组预定循环计数的预定计数时，用选定的冗余电路替换先前选择的冗余电路。

公开(公告)号：US20090109781A1

公开(公告)日：2009-04-30

申请号：US11924935

申请日：2007-10-26

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C7/00

CPC分类号： G06F12/121 ,  G06F2212/1056 ,  G11C7/1006

摘要： An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge storing device by a charge source; and means for measuring a potential of the charge storing device, the measuring means being communicatively coupled to a calculating mean which determines a relative amount of usage of the data retaining device based on the measured potential.

摘要翻译： 公开了集成电路和设计结构。 集成电路可以包括：数据保持装置; 电荷存储装置，其耦合到数据保持装置，使得数据保持装置的使用触发电荷源对电荷存储装置的充电; 以及用于测量电荷存储装置的电位的装置，所述测量装置通信地耦合到基于所测量的电位确定数据保持装置的相对使用量的计算平均值。

公开(公告)号：US20090031111A1

公开(公告)日：2009-01-29

申请号：US11828705

申请日：2007-07-26

申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, JR. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3897 ,  G06F15/7867

摘要： A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performance of the static instructions and the dynamic instructions is evaluated based on current states of the execution units. The static instructions or the dynamic instructions are selected for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

摘要翻译： 一种方法，装置和计算机程序产品动态地选择编译指令进行执行。 接收用于在第一执行上执行的静态指令和用于在第二执行单元上执行的动态指令。 基于执行单元的当前状态来评估静态指令和动态指令的吞吐量性能。 基于指令的吞吐量性能，静态指令或动态指令分别被选择用于在运行时在第一执行单元或第二执行单元上执行。