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公开(公告)号：US20100164542A1
公开(公告)日：2010-07-01
申请号：US12722317
申请日：2010-03-11
申请人： Yasuhiro AGATA , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
发明人： Yasuhiro AGATA , Toshiaki Kawasaki , Masanori Shirahama , Ryuji Nishihara , Shinichi Sumi , Yasue Yamamoto , Hirohito Kikukawa
IPC分类号： H03K19/173
CPC分类号： G11C5/063 , G11C5/14 , G11C17/165 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.
摘要翻译： 系统LSI包括输入/输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。
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公开(公告)号：US20080186789A1
公开(公告)日：2008-08-07
申请号：US12021317
申请日：2008-01-29
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： A first transistor is connected in series with one end of a fuse element. A second transistor is connected in series with the other end of the fuse element. A current flows through the fuse element when both the first and second transistors are turned on.
摘要翻译： 第一晶体管与保险丝元件的一端串联连接。 第二晶体管与保险丝元件的另一端串联连接。 当第一和第二晶体管都导通时，电流流过熔丝元件。
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公开(公告)号：US20060158920A1
公开(公告)日：2006-07-20
申请号：US11324243
申请日：2006-01-04
IPC分类号： G11C17/00
CPC分类号： G11C17/18
摘要： An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.
摘要翻译： 本发明的电熔丝电路包括多个电熔丝芯（1），每个电熔丝芯具有彼此串联连接的电熔丝元件（3）和开关晶体管（4），并且移位寄存器（2）连接 到多个电熔丝芯（1）以编程电熔丝元件（3）。 程序使能信号（Si）由移位寄存器（2）依次产生和传送，开关晶体管（4）根据程序使能信号（Si）和程序数据（Di）的信息依次导通， 电熔丝元件（3）被一个接一个地吹出。
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公开(公告)号：US07254079B2
公开(公告)日：2007-08-07
申请号：US11324243
申请日：2006-01-04
CPC分类号： G11C17/18
摘要： An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.
摘要翻译： 本发明的电熔丝电路包括多个电熔丝芯（1），每个电熔丝芯具有彼此串联连接的电熔丝元件（3）和开关晶体管（4），并且移位寄存器（2）连接 到多个电熔丝芯（1）以编程电熔丝元件（3）。 程序使能信号（Si）由移位寄存器（2）依次产生和传送，开关晶体管（4）根据程序使能信号（Si）和程序数据（Di）的信息依次导通， 电熔丝元件（3）被一个接一个地吹出。
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公开(公告)号：US07622982B2
公开(公告)日：2009-11-24
申请号：US11882974
申请日：2007-08-08
IPC分类号： H01H37/76
摘要： The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.
摘要翻译： 本发明提供一种电熔丝装置，包括：多个熔丝芯，每个熔丝芯具有电熔丝元件和串联连接到电熔丝元件的开关元件; 程序控制电路，通过与有效的程序时钟信号同步地依次移位程序控制传输信号并随后根据程序数据产生要发送到多个保险丝核心中的每一个开关元件的程序信号来产生程序移位信号 和程序移位信号; 以及程序时钟控制电路，其根据程序时钟使能信号控制编程时钟信号的导通状态和非导通状态，并且当所述程序时钟信号处于导通状态时，将所述程序时钟信号发送到所述程序控制电路 作为有效的程序时钟信号。
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公开(公告)号：US20080036527A1
公开(公告)日：2008-02-14
申请号：US11882974
申请日：2007-08-08
IPC分类号： H01H37/76
摘要： The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.
摘要翻译： 本发明提供一种电熔丝装置，包括：多个熔丝芯，每个熔丝芯具有电熔丝元件和串联连接到电熔丝元件的开关元件; 程序控制电路，通过与有效的程序时钟信号同步地依次移位程序控制传输信号并随后根据程序数据产生要发送到多个保险丝核心中的每一个开关元件的程序信号来产生程序移位信号 和程序移位信号; 以及程序时钟控制电路，其根据程序时钟使能信号控制编程时钟信号的导通状态和非导通状态，并且当所述程序时钟信号处于导通状态时，将所述程序时钟信号发送到所述程序控制电路 作为有效的程序时钟信号。
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公开(公告)号：US06765814B2
公开(公告)日：2004-07-20
申请号：US10315042
申请日：2002-12-10
申请人： Ryuji Nishihara , Hiroyuki Sadakata
发明人： Ryuji Nishihara , Hiroyuki Sadakata
IPC分类号： G11C506
摘要： Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines. Thereby, it becomes unnecessary to separately provide strapping regions at the ends of memory cell array portions and it becomes unnecessary to increase the intervals between the memory cells by increasing the size of the memory cell in the layout according to the standard CMOS process and, therefore, contacts for strapping word lines can be provided for each memory cell, without increasing the area of memory cell array portions or the chip area, so that the propagation delay of drive signals in word lines can be reduced and high speed memory operation can be implemented.
摘要翻译： 带状线设置在字线上方的层中，使得字线和带线彼此连接在具有问题的常规半导体存储器件中的分开设置在存储单元阵列部分的端部处的带状区域中，其中， 存储单元阵列部分增加。 根据标准CMOS工艺，每个存储单元由存储单元阵列部分的布局中的MOS晶体管和MOS电容器形成。 这种结构的存储单元在位线之间具有足够大的间距，因此，用于将字线连接到上层中的带线的触点设置在与位线相同的层中作为低电阻金属线的位线 。 因此，不需要在存储单元阵列部分的端部分开提供带状区域，并且不需要通过根据标准CMOS工艺增加布局中的存储单元的尺寸来增加存储单元之间的间隔，因此 可以为每个存储单元提供用于捆扎字线的触点，而不增加存储单元阵列部分或芯片面积的面积，从而可以减少字线中的驱动信号的传播延迟并且可以实现高速存储器操作 。
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