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5 条记录 (耗时 0.024 秒)

    SYSTEM LSI
    1.
    发明申请
    SYSTEM LSI 有权
    系统LSI

    公开(公告)号：US20100164542A1

    公开(公告)日：2010-07-01

    申请号：US12722317

    申请日：2010-03-11

    申请人： Yasuhiro AGATA ,  Toshiaki Kawasaki ,  Masanori Shirahama ,  Ryuji Nishihara ,  Shinichi Sumi ,  Yasue Yamamoto ,  Hirohito Kikukawa

    发明人： Yasuhiro AGATA ,  Toshiaki Kawasaki ,  Masanori Shirahama ,  Ryuji Nishihara ,  Shinichi Sumi ,  Yasue Yamamoto ,  Hirohito Kikukawa

    IPC分类号： H03K19/173

    CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C17/165 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system LSI includes an input/output section and a logic circuit section. The input/output section includes an I/O power source cell having a supply voltage higher than a power source for the logic circuit section and a plurality of I/O cells in each of which an I/O power source line is provided for supplying source power from the I/O power source cell. The logic circuit section includes an I/O power consuming circuit which uses the I/O power source cell as a power source. The I/O power consuming circuit is connected to a line leading from an I/O power source line in at least one of the plurality of I/O cells.

    摘要翻译： 系统LSI包括输入/​​输出部分和逻辑电路部分。 输入/输出部分包括具有高于用于逻辑电路部分的电源的电源电压的I / O电源单元和设置有I / O电源线的多个I / O单元，用于提供 来自I / O电源单元的源电源。 逻辑电路部分包括使用I / O电源单元作为电源的I / O功耗电路。 I / O消耗电路连接到从多个I / O单元中的至少一个中的I / O电源线引出的线。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20080205144A1

    公开(公告)日：2008-08-28

    申请号：US11971334

    申请日：2008-01-09

    申请人： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    发明人： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    IPC分类号： G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

    摘要翻译： 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20100238735A1

    公开(公告)日：2010-09-23

    申请号：US12792295

    申请日：2010-06-02

    申请人： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    发明人： Yasue YAMAMOTO ,  Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Toshiaki KAWASAKI

    IPC分类号： G11C16/04 ,  H01L29/94

    CPC分类号： G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

    摘要翻译： 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

    Semiconductor memory device
    4.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20080112210A1

    公开(公告)日：2008-05-15

    申请号：US11905532

    申请日：2007-10-02

    申请人： Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Yasue YAMAMOTO

    发明人： Masanori SHIRAHAMA ,  Yasuhiro AGATA ,  Yasue YAMAMOTO

    IPC分类号： G11C11/00 ,  G11C8/00

    CPC分类号： G11C11/16 ,  G11C7/12 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0028 ,  G11C2213/72

    摘要： A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.

    摘要翻译： 存储单元通过串联连接可变电阻元件，该可变电阻元件具有通过使用其另一端子处的电位作为参考而将正电压施加到其一个端子（第一节点）而变化的电阻，以及允许 使用在其一个端子（第二节点）处的电位作为参考，通过向其另一端施加正电压而流过其中的电流。 第一个节点连接到相应的列选择线，第二个节点连接到相应的行选择行。 然后，对于未选择的行选择线，通过使用行控制电路来应用比选择行选择线高的电位。 通过使用列选择线驱动电路，将对应于非选择周期，数据写入周期，复位周期和数据读取周期的预定电位施加到列选择线。