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21.发明授权Method of generating a chaos-based pseudo-random sequence and a hardware generator of chaos-based pseudo random bit sequences 有权一种基于混沌的伪随机序列的生成方法和基于混沌伪随机比特序列的硬件生成器公开(公告)号：US07779060B2
公开(公告)日：2010-08-17
申请号：US10712988
申请日：2003-11-12
申请人： Ljupco Kocarev , Paolo Amato , Gianguido Rizzotto
发明人： Ljupco Kocarev , Paolo Amato , Gianguido Rizzotto
IPC分类号： G06F1/02
CPC分类号： H04L9/001 , G06F7/582 , H04L9/0662 , H04L2209/20
摘要： A method for generating cryptographically secure (or unpredictable) pseudo-random numbers uses simple functions whose inverse is not a well-defined function and has a large number of branches, although the inverse could be easily computed on each particular branch. In this way the sequence of numbers is practically unpredictable and at the same time may be generated using very simple functions. A generator of such a pseudo-random bit sequence comprises circuit means for storing bit strings representing integer numbers of the pseudo-random sequence; a shift register coupled to the circuit means; a command circuit generating shift commands for the shift register; second circuit means for storing the bits output by the shift register; an adder modulo 2 summing the bits stored in the second circuit means, generating a bit of the chaos-based pseudo-random bit sequence; a second adder summing up the bit strings currently stored in the shift register and in the first circuit means, generating a bit string representing a successive number of the pseudo-random sequence.
摘要翻译： 用于生成加密安全（或不可预测）伪随机数的方法使用简单函数，其逆并不是明确定义的函数，并且具有大量的分支，尽管可以在每个特定分支上容易地计算逆。 以这种方式，数字序列实际上是不可预测的，同时可以使用非常简单的功能来产生。 这种伪随机比特序列的生成器包括用于存储表示整数个伪随机序列的比特串的电路装置; 耦合到所述电路装置的移位寄存器; 产生移位寄存器的移位指令的指令电路; 第二电路装置，用于存储由移位寄存器输出的位; 加法器模2将存储在第二电路装置中的比特相加，产生基于混沌的伪随机比特序列的比特; 第二加法器对当前存储在移位寄存器和第一电路装置中的位串进行相加，生成表示连续数量的伪随机序列的比特串。
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22.发明申请Hosting structure of nanometric elements and corresponding manufacturing method 有权纳米元素的主机结构及相应的制造方法公开(公告)号：US20070176208A1
公开(公告)日：2007-08-02
申请号：US11215348
申请日：2005-08-30
IPC分类号： H01L27/10
CPC分类号： H01L51/0021 , G11C2213/77 , H01L27/285 , H01L51/0595 , Y10S257/90 , Y10S977/712 , Y10S977/72 , Y10S977/722 , Y10S977/723
摘要： A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.
摘要翻译： 描述了纳米级元件的托管结构，其包括衬底，第一多间隔物层，包括第一多个间隔物，其包括彼此平行的第一导电间隔物，以及在所述第一多间隔物层上方实现的至少第二多间隔物水平 并且包括横向于所述第一多个间隔件布置的第二多个间隔件，并且至少包括下部不连续绝缘层和上层，其又包括第二导电间隔件。 特别地，第二多间隔物级别的每对间隔物限定第一多间隔物层的间隔物，多个纳米托管座具有至少第一和第二导电端子，该第一和第二导电端子由第一导电间隔物的部分实现， 的第二导电隔离物面向主机座。 还描述了制造这种结构的方法。
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公开(公告)号：US07069282B2
公开(公告)日：2006-06-27
申请号：US10167058
申请日：2002-06-11
申请人： Gianguido Rizzotto , Paolo Amato , Domenico Porto
发明人： Gianguido Rizzotto , Paolo Amato , Domenico Porto
CPC分类号： G06N99/002 , B82Y10/00
摘要： A quantum gate performs the superposition operation of a Grover's or of a Deutsch-Jozsa's quantum algorithm in a very fast manner. This is done by performing all multiplications by using logic gates that immediately outputs the result. The superposition operation includes performing the Hadamard rotation over an input set of vectors for producing a set of rotated vectors, and calculating the tensor product of all the rotated vectors for outputting a linear superposition set of vectors. The tensor product of all the rotated vectors is carried out by the logic gates.
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公开(公告)号：US07834344B2
公开(公告)日：2010-11-16
申请号：US11215296
申请日：2005-08-30
CPC分类号： H01L51/0021 , H01L51/0595 , Y10S977/712 , Y10S977/781
摘要： A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.
摘要翻译： 描述了纳米组件的托管结构，其有利地包括：衬底; 所述衬底上具有n≥2的n个阵列电平在生长和平行平面上连续布置，每个平面包括多个导电间隔物，其与多个绝缘间隔物交替并且基本上垂直于所述衬底，并且在至少 间隙，位于不同平行平面上的连续阵列电平的导电间隔物，所述不同阵列电平的所述间隙沿着基本上垂直于所述衬底的方向至少部分地对准，定义了沿着所述方向延伸的多个横向主持座，并且适合 用于托管至少一个纳米元件。 还描述了一种纳米电子设备，其包括这样的托管结构和用于实现它的方法。
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公开(公告)号：US20090020747A1
公开(公告)日：2009-01-22
申请号：US12204688
申请日：2008-09-04
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
摘要翻译： 一种纳米装置，包括基底; 导电材料的多个导电间隔物，每个导电间隔物布置在衬底的顶部并横向于衬底，导电间隔物包括相应的一对导电间隔物，每个导电间隔物限定各自的托架座位，每个主体座椅的宽度小于30nm; 以及分别容纳在托管座椅中的多个纳米元件。
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26.发明授权Hosting structure of nanometric elements and corresponding manufacturing method 有权纳米元素的主机结构及相应的制造方法公开(公告)号：US07456508B2
公开(公告)日：2008-11-25
申请号：US11215348
申请日：2005-08-30
IPC分类号： H01L27/10
CPC分类号： H01L51/0021 , G11C2213/77 , H01L27/285 , H01L51/0595 , Y10S257/90 , Y10S977/712 , Y10S977/72 , Y10S977/722 , Y10S977/723
摘要： A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.
摘要翻译： 描述了纳米级元件的托管结构，其包括衬底，第一多间隔物层，包括第一多个间隔物，其包括彼此平行的第一导电间隔物，以及在所述第一多间隔物层上方实现的至少第二多间隔物水平 并且包括横向于所述第一多个间隔件布置的第二多个间隔件，并且至少包括下部不连续绝缘层和上层，其又包括第二导电间隔件。 特别地，第二多间隔物级别的每对间隔物限定第一多间隔物层的间隔物，多个纳米托管座具有至少第一和第二导电端子，该第一和第二导电端子由第一导电间隔物的部分实现， 的第二导电隔离物面向主机座。 还描述了制造这种结构的方法。
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公开(公告)号：US07106864B2
公开(公告)日：2006-09-12
申请号：US10319432
申请日：2002-12-12
CPC分类号： H04L9/001 , H04L9/002 , H04L9/0618 , H04L2209/24
摘要： In an encryption/decryption system for converting data signals between an unencrypted plaintext format and an encrypted ciphertext format plurality of round modules are provided permitting a respective set of input data signals (TEXT IN) to generate a respective set of output data signals (TEXT OUT) by means of transformation controlled by a round key (SUBKEY). The transformation is identified by at least one map function derived from a chaotic map.
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公开(公告)号：US20060051946A1
公开(公告)日：2006-03-09
申请号：US11215297
申请日：2005-08-30
IPC分类号： H01L21/3205 , H01L21/20
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n≧2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.
摘要翻译： 制造纳米元件的托盘结构的方法，包括以下步骤：在第一材料的基片的上表面上沉积具有至少一个侧壁的块状晶种。 在至少一部分的悲伤表面上和块状种子上沉积具有预定厚度的第二材料的第一层，并随后选择性地和各向异性地蚀刻它以形成邻近侧壁的间隔物种子。 重复n次（n> = 2）预定材料的沉积循环和选择性蚀刻步骤，每个循环中形成至少一个间隔物。 该预定材料对于每对连续沉积物是不同的。 上述n个步骤提供至少一个多层体。 进一步的选择性蚀刻除去每隔一个间隔物以提供多个纳米托管座，其形成托管在所述托管座中的多个分子晶体管的接触端子。
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29.发明授权Method and an apparatus for reducing noise of the pulsive type in digital video receiver sets 失效用于减少数字视频接收机中脉冲类型噪声的方法和装置
公开(公告)号：US5196935A
公开(公告)日：1993-03-23
申请号：US630511
申请日：1990-12-20
IPC分类号： H04N5/213
CPC分类号： H04N5/213
摘要： The invention relates to a method for reducing noise of the pulsive type in digital video receiver sets. The method consists of picking up a noise-affected sample of a video signal and replacing it with a weighted average of samples located in the contour thereof; this allows the noise component to be fittered out with a lower load, in terms of circuit complexity, on the TV set.
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公开(公告)号：US07952173B2
公开(公告)日：2011-05-31
申请号：US12204688
申请日：2008-09-04
IPC分类号： H01L29/06
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
摘要翻译： 一种纳米装置，包括基底; 导电材料的多个导电间隔物，每个导电间隔物布置在衬底的顶部并横向于衬底，导电间隔物包括相应的一对导电间隔物，每个导电间隔物限定各自的托架座位，每个主体座椅的宽度小于30nm; 以及分别容纳在托管座椅中的多个纳米元件。
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