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    Thin film transistor having a plurality of carbon nanotubes
    4.
    发明授权
    Thin film transistor having a plurality of carbon nanotubes 有权
    具有多个碳纳米管的薄膜晶体管

    公开(公告)号：US08101953B2

    公开(公告)日：2012-01-24

    申请号：US12384329

    申请日：2009-04-02

    Applicant: Kai-Li Jiang ,  Qun-Qing Li ,  Shou-Shan Fan

    Inventor： Kai-Li Jiang ,  Qun-Qing Li ,  Shou-Shan Fan

    IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/108 ,  H01L29/04 ,  H01L29/12 ,  H01L31/0376 ,  H01L31/20

    CPC classification number: H01L51/0012 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/0562 ,  Y10S977/723 ,  Y10S977/842 ,  Y10S977/938

    Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes at least two stacked carbon nanotube films. Each carbon nanotube film includes an amount of carbon nanotubes. At least a part of the carbon nanotubes of each carbon nanotube film are aligned along a direction from the source electrode to the drain electrode.

    Abstract translation: 薄膜晶体管包括源电极，漏电极，半导体层和栅电极。 漏电极与源电极间隔开。 半导体层连接到源电极和漏电极。 栅电极通过绝缘层与源电极，漏电极和半导体层绝缘。 半导电层包括至少两个堆叠的碳纳米管膜。 每个碳纳米管膜包括一定量的碳纳米管。 每个碳纳米管膜的碳纳米管的至少一部分沿着从源电极到漏电极的方向排列。

    Sieving media from planar arrays of nanoscale grooves, method of making and method of using the same
    5.
    发明授权
    Sieving media from planar arrays of nanoscale grooves, method of making and method of using the same 有权
    从纳米级槽的平面阵列筛分介质，制备方法及其使用方法

    公开(公告)号：US08088282B2

    公开(公告)日：2012-01-03

    申请号：US13023807

    申请日：2011-02-09

    Applicant: Scott Sibbett

    Inventor： Scott Sibbett

    IPC: B01D15/34 ,  B01D15/08

    CPC classification number: G01N30/0005 ,  B01D67/0062 ,  G01N27/44756 ,  Y10S977/701 ,  Y10S977/72 ,  Y10S977/723 ,  Y10T137/87249 ,  G01N30/6095

    Abstract: Disclosed herein are an apparatus and a method for separating molecules on the basis of size and or structure, and to a method of making the apparatus. Generally, the separation method includes passing a fluid comprising particles having different effective molecular diameters through a plurality of open, nanoscale channels disposed in surfaces of substrates. The method also includes obtaining a plurality of fractions of the passed fluid such that each of the fractions includes a major portion containing particles having similar size and shape and substantially free of particles having larger size and shape. The apparatus includes first and second substrates each of which has a surface containing a plurality of open, nanoscale channels disposed therein. The surfaces are bonded together such that each of the channels of the first substrate is in fluid communication with at least two of the channels of the second substrate and is misaligned relative to the channels of the second substrate. Interferometric lithography and anodic bonding or flip-chip bonding techniques can be used to make the apparatus.

    Abstract translation: 本文公开了基于尺寸和/或结构分离分子的装置和方法，以及制造该装置的方法。 通常，分离方法包括使包含具有不同有效分子直径的颗粒的流体通过设置在基材表​​面中的多个开放的纳米级通道。 该方法还包括获得通过的流体的多个部分，使得每个级分包含主要部分，其含有具有相似尺寸和形状的颗粒，并且基本上不含具有较大尺寸和形状的颗粒。 该装置包括第一和第二基板，每个基板具有包含设置在其中的多个开放的纳米级通道的表面。 表面被接合在一起，使得第一基底的每个通道与第二基底的至少两个通道流体连通，并且相对于第二基底的通道不对准。 可以使用干涉光刻和阳极结合或倒装芯片接合技术来制造该装置。

    Drive method of nanogap switching element and storage apparatus equipped with nanogap switching element
    6.
    发明授权
    Drive method of nanogap switching element and storage apparatus equipped with nanogap switching element 有权
    纳米开关元件的驱动方法和配备纳米角开关元件的存储装置

    公开(公告)号：US07990751B2

    公开(公告)日：2011-08-02

    申请号：US12338313

    申请日：2008-12-18

    Applicant: Yuichiro Masuda ,  Shigeo Furuta ,  Tsuyoshi Takahashi ,  Tetsuo Shimizu ,  Yasuhisa Naitoh ,  Masayo Horikawa

    Inventor： Yuichiro Masuda ,  Shigeo Furuta ,  Tsuyoshi Takahashi ,  Tetsuo Shimizu ,  Yasuhisa Naitoh ,  Masayo Horikawa

    IPC: G11C11/00 ,  G11C13/00 ,  G11C7/00 ,  G11C7/22

    CPC classification number: G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/009 ,  Y10S977/708 ,  Y10S977/723 ,  Y10S977/94 ,  Y10S977/943

    Abstract: A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element is shifted from its low resistance state to its high resistance state by receiving a voltage pulse application of a first voltage value, and shifted from its high resistance state to its low resistance state by receiving a voltage pulse application of a second voltage value lower than the first voltage value. When the nanogap switching element is shifted from the high resistance state to the low resistance state, a voltage pulse of an intermediate voltage value between the first and second voltage values is applied thereto before the voltage pulse application of the second voltage value thereto.

    Abstract translation: 纳米点开关元件配备有包括第一电极和第二电极之间的纳米级间隙的电极间间隙部分。 通过在第一和第二电极之间施加电压，在电极间间隙部分产生切换现象。 纳米点开关元件通过接收第一电压值的电压脉冲而从其低电阻状态转移到其高电阻状态，并且通过接收施加第二电压的电压脉冲从其高电阻状态转移到其低电阻状态 值低于第一电压值。 当纳米点开关元件从高电阻状态移动到低电阻状态时，在施加第二电压值的电压脉冲之前，施加第一和第二电压值之间的中间电压值的电压脉冲。

    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS
    8.
    发明申请
    SYSTEMS AND METHODS FOR FABRICATION OF SUPERCONDUCTING INTEGRATED CIRCUITS 有权
    超导集成电路制造系统与方法

    公开(公告)号：US20110089405A1

    公开(公告)日：2011-04-21

    申请号：US12992049

    申请日：2010-02-25

    Applicant: Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

    Inventor： Eric Ladizinsky ,  Geordie Rose ,  Jeremy P. Hilton ,  Eugene Dantsker ,  Byong Hyop Oh

    IPC: H01L39/22 ,  H01L39/24

    CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L28/24 ,  H01L39/025 ,  H01L39/223 ,  H01L39/2406 ,  H01L39/2493 ,  Y10S977/707 ,  Y10S977/723 ,  Y10S977/943

    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

    Abstract translation: 各种技术和设备允许制造超导电路和结构，例如约瑟夫逊结，其可以例如在量子计算机中有用。 例如，可以制造具有插入在能够超导的两个元件或层之间的电介质结构或层的低磁通量噪声三层结构。 超导通孔可以直接覆盖约瑟夫逊结。 诸如约瑟夫逊结的结构可以承载在平坦化的电介质层上。 可以使用翅片来除去结构中的热量。 能够超导的通孔可以具有小于约1微米的宽度。 该结构可以例如通过通孔和/或带连接器耦合到电阻器。

    Sieving media from planar arrays of nanoscale grooves, method of making and method of using the same
    9.
    发明授权
    Sieving media from planar arrays of nanoscale grooves, method of making and method of using the same 有权
    从纳米级槽的平面阵列筛分介质，制备方法及其使用方法

    公开(公告)号：US07906026B2

    公开(公告)日：2011-03-15

    申请号：US12315219

    申请日：2008-12-01

    Applicant: Scott Sibbett

    Inventor： Scott Sibbett

    IPC: B01D15/34 ,  B01D63/08

    CPC classification number: G01N30/0005 ,  B01D67/0062 ,  G01N27/44756 ,  Y10S977/701 ,  Y10S977/72 ,  Y10S977/723 ,  Y10T137/87249 ,  G01N30/6095

    Abstract: Disclosed herein are an apparatus and a method for separating molecules on the basis of size and or structure, and to a method of making the apparatus. Generally, the separation method includes passing a fluid comprising particles having different effective molecular diameters through a plurality of open, nanoscale channels disposed in surfaces of substrates. The method also includes obtaining a plurality of fractions of the passed fluid such that each of the fractions includes a major portion containing particles having similar size and shape and substantially free of particles having larger size and shape. The apparatus includes first and second substrates each of which has a surface containing a plurality of open, nanoscale channels disposed therein. The surfaces are bonded together such that each of the channels of the first substrate is in fluid communication with at least two of the channels of the second substrate and is misaligned relative to the channels of the second substrate. Interferometric lithography and anodic bonding or flip-chip bonding techniques can be used to make the apparatus.

    Abstract translation: 本文公开了基于尺寸和/或结构分离分子的装置和方法，以及制造该装置的方法。 通常，分离方法包括使包含具有不同有效分子直径的颗粒的流体通过设置在基材表​​面中的多个开放的纳米级通道。 该方法还包括获得通过的流体的多个部分，使得每个级分包含主要部分，其含有具有相似尺寸和形状的颗粒，并且基本上不含具有较大尺寸和形状的颗粒。 该装置包括第一和第二基板，每个基板具有包含设置在其中的多个开放的纳米级通道的表面。 表面被接合在一起，使得第一基底的每个通道与第二基底的至少两个通道流体连通，并且相对于第二基底的通道不对准。 可以使用干涉光刻和阳极结合或倒装芯片接合技术来制造该装置。

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