公开(公告)号：US20240256463A1

公开(公告)日：2024-08-01

申请号：US18629470

申请日：2024-04-08

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/10 ,  G06F12/0253 ,  G06F2212/1044 ,  G06F2212/657

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

公开(公告)号：US11810630B2

公开(公告)日：2023-11-07

申请号：US17523523

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N20/00 ,  G11C29/18 ,  G11C16/26 ,  G06F18/21 ,  G06F18/243

CPC classification number: G11C16/3495 ,  G06F18/2178 ,  G06F18/24323 ,  G06N20/00 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C29/18

Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

公开(公告)号：US20230214298A1

公开(公告)日：2023-07-06

申请号：US18184395

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0679

Abstract: An error associated with host data written to a page of a storage area of a memory sub-system is detected. A determination is made that parity data corresponding to the host data is stored in a cache memory of the memory sub-system. A data recovery operation is performed based on the parity data stored in the cache memory.

公开(公告)号：US20230161712A1

公开(公告)日：2023-05-25

申请号：US18094744

申请日：2023-01-09

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/10 ,  G06F12/0253 ,  G06F2212/1044 ,  G06F2212/657

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

公开(公告)号：US11609848B2

公开(公告)日：2023-03-21

申请号：US16943143

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/02 ,  G06F12/1009

Abstract: A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

公开(公告)号：US20230061920A1

公开(公告)日：2023-03-02

申请号：US17523523

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/18 ,  G06K9/62 ,  G06N20/00

Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

公开(公告)号：US11593018B2

公开(公告)日：2023-02-28

申请号：US17381945

申请日：2021-07-21

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

Abstract: A plurality of zone reset counters and a global reset counter are maintained. A zone reset counter represents a number of times a respective zone of a memory device has been reset. The global reset counter represents a measure of central tendency of the plurality of zone reset counters. A write command directed to a target zone of the memory device is received, and responsive to determining that a target portion of the target zone is not open, a value of the zone reset counter of het target zone is compared to the value of the global reset counter. If the value of the target zone reset counter equals or exceeds the value of the global reset counter, a portion from a free block list is allocated to the target zone. The allocated portion has a highest program erase count among the one or more portions in free block list.

公开(公告)号：US11550727B2

公开(公告)日：2023-01-10

申请号：US16946377

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/10 ,  G06F12/02

Abstract: Disclosed is a system including a memory device having a plurality of physical memory blocks and associated with a logical address space that comprises a plurality of zones, wherein each zone comprises a plurality of logical block addresses (LBAs), and a processing device, operatively coupled with the memory device, to perform operations of receiving a request to store data referenced by an LBA associated with a first zone of the plurality of zones, obtaining a version identifier of the first zone, obtaining erase values for a plurality of available physical memory blocks of the memory device, selecting, in view of the version identifier of the first zone and the erase values, a first physical memory block of the plurality of available physical memory blocks, mapping a next available LBA within the first zone to the first physical memory block, and storing the data in the first physical memory block.

公开(公告)号：US20220382681A1

公开(公告)日：2022-12-01

申请号：US17887300

申请日：2022-08-12

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/1009

Abstract: A write request is determined to comprise at least a partial translation unit. A size of the partial translation unit is smaller than a size of a predefined translation unit. A first entry in a translation map is identified. The translation map maps a plurality of translation units to a plurality of physical blocks. The first entry identifies a first physical block corresponding to the predefined translation unit. A second entry in the translation map is created. The second entry identifies a second physical block. An association between the first entry and the second entry is created, such that the second entry corresponds to the predefined translation unit. A write operation is performed to write a set of data corresponding to the partial translation unit to the second physical block.