公开(公告)号：US20230176764A1

公开(公告)日：2023-06-08

申请号：US18101722

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0644 ,  G06F3/0616 ,  G06F3/0659

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

公开(公告)号：US20220319622A1

公开(公告)日：2022-10-06

申请号：US17218385

申请日：2021-03-31

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/40 ,  G11C29/00

Abstract: Disclosed is a system that comprises a memory device comprising a plurality of memory planes and a processing device, operatively coupled with the memory device, to perform operations that include, generating a block stripe of the memory device, wherein the block stripe comprises a plurality of blocks arranged across the plurality of memory planes; determining that a first block of the plurality of blocks of the block stripe is associated with an error condition, wherein the first block is associated with a first plane of the plurality of planes; and responsive to determining that the first block of the plurality of blocks of the block stripe is associated with the error condition, performing an error recovery operation on the plurality of blocks to replace the first block with a replacement block in the block stripe.

公开(公告)号：US20220035735A1

公开(公告)日：2022-02-03

申请号：US16943143

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/02 ,  G06F12/1009

Abstract: A number of data access operations is tracked where the data access operations are associated with each of a plurality of portions of a translation map. The translation map maps a plurality of logical block addresses to a plurality of physical block addresses of the memory device. A criterion to perform a garbage collection operation is determined to be satisfied. The garbage collection operation is to be performed on a block of the memory component. The block for performing the garbage collection operation is identified based on the number of data access operations associated with each of the plurality of portions of the translation map. The garbage collection operation is performed on the identified block.

公开(公告)号：US12189973B2

公开(公告)日：2025-01-07

申请号：US18101722

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

Abstract: A write command directed to a target zone of a memory device is received. Responsive to determining that a first portion of the target zone is open, the write command is executed at the first portion. Responsive to determining that the first portion has reached a threshold capacity, a second portion allocated to a media management pool is identified. The second portion satisfies a threshold capacity. One or more blocks associated with the second portion are erased. The second portion is allocated to a free block list.

公开(公告)号：US20230176965A1

公开(公告)日：2023-06-08

申请号：US18106670

申请日：2023-02-07

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0253 ,  G06F12/1009 ,  G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7205 ,  G06F2212/7208 ,  G06F2212/7201

Abstract: A system includes: a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: dividing a translation map into a plurality of portions of the translation map, the translation map mapping a plurality of logical block addresses to a plurality of physical block addresses of the memory device, each of the plurality of portions of the translation map corresponding to a plurality of blocks of the memory device, wherein a portion of the plurality of portions of the translation map comprises a plurality of entries, each entry mapping a logical block address to a physical block address of the memory device; updating, responsive to receiving a data access request, a counter of data access operations performed using each of the plurality of portions of the translation map; responsive to determining that a predefined condition is satisfied, identifying a portion of the plurality of portions of the translation map based on the counter of data access operations; identifying a block among a plurality of blocks of the memory device corresponding to the identified portion of the translation map; and performing a garbage collection operation on the identified block.

公开(公告)号：US11467976B2

公开(公告)日：2022-10-11

申请号：US16943387

申请日：2020-07-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/1009

Abstract: A write request is determined to comprise at least a partial translation unit. A size of the partial translation unit is smaller than a size of a predefined translation unit. A first entry in a translation map is identified. The translation map maps a plurality of translation units to a plurality of physical blocks. The first entry identifies a first physical block corresponding to the predefined translation unit. A second entry in the translation map is created. The second entry identifies a second physical block. An association between the first entry and the second entry is created, such that the second entry corresponds to the predefined translation unit. A write operation is performed to write a set of data corresponding to the partial translation unit to the second physical block.

公开(公告)号：US20220019370A1

公开(公告)日：2022-01-20

申请号：US16930922

申请日：2020-07-16

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

Abstract: A request to perform a write operation to write data at a memory device configured with a zoned namespace having multiple zones is received. The data is associated with a zone of the multiple zones of the memory device. The data is stored at a non-zoned memory unit of a non-zoned memory region of the memory device. Whether the amount of data stored at the non-zoned memory unit and associated with the zone satisfies a threshold condition is determined. Responsive to determining that the data stored at the non-zoned memory unit and associated with the zone satisfies the threshold condition, the data is written from the non-zoned memory unit to a zone memory unit of the zone.

公开(公告)号：US20210191808A1

公开(公告)日：2021-06-24

申请号：US16834534

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj ,  Naveen Bolisetty ,  Suman Kumari

IPC: G06F11/10 ,  G06F12/0882 ,  G06F12/02 ,  G06F9/30

Abstract: Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

公开(公告)号：US20250147896A1

公开(公告)日：2025-05-08

申请号：US19014012

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F12/1009

Abstract: An example system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including: determining that a write request references a partially aligned translation unit; identifying a first entry in a translation map, such that the first entry identifies a first physical block of the memory device, such that the first physical block is mapped to the partially aligned translation unit; creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit; linking, in the translation map, the first entry and the second entry; and writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.

公开(公告)号：US20250130734A1

公开(公告)日：2025-04-24

申请号：US19007911

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G06F3/06

Abstract: A reset counter associated with a zone of the memory device is maintained. The reset counter represents a number of times the zone has been reset. In response to receiving a write command directed to the zone of the memory device, a target portion of the zone that is not open is identified. A first portion from a free portion list is identified. The program erase count of the first portion corresponds to the reset counter associated with the zone. The first portion is allocated to the zone.