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公开(公告)号：US20230176776A1
公开(公告)日：2023-06-08
申请号：US17457202
申请日：2021-12-01
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Olivier Duval
CPC classification number: G06F3/0659 , G06F3/0664 , G06F3/0613 , G06F3/0673 , G06F9/45558 , G06F2009/45583
Abstract: Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.
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公开(公告)号：US11513923B2
公开(公告)日：2022-11-29
申请号：US16452344
申请日：2019-06-25
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Christopher Joseph Bueb
Abstract: A solid state drive having a drive aggregator and a plurality of component solid state drive, including a first component solid state drive and a second component solid state drive. The drive aggregator has at least one host interface, and a plurality of drive interfaces connected to the plurality of component solid state drives. The drive aggregator is configured to generate, in the second solid state drive, a copy of a dataset that is stored in the first component solid state drive. In response to a failure of the first component solid state drive, the drive aggregator is configured to substitute a function of the first component solid state drive with respect to the dataset with a corresponding function of the second component solid state drive, based on the copy of the dataset generated in the second component solid state drive.
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公开(公告)号：US11296729B2
公开(公告)日：2022-04-05
申请号：US16937077
申请日：2020-07-23
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Christopher Joseph Bueb
Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.
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公开(公告)号：US20220029641A1
公开(公告)日：2022-01-27
申请号：US16937077
申请日：2020-07-23
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Christopher Joseph Bueb
Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.
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公开(公告)号：US20210271622A1
公开(公告)日：2021-09-02
申请号：US17326141
申请日：2021-05-20
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Poorna Kale
Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20210157719A1
公开(公告)日：2021-05-27
申请号：US17170766
申请日：2021-02-08
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Poorna Kale
Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.
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公开(公告)号：US20250006241A1
公开(公告)日：2025-01-02
申请号：US18759484
申请日：2024-06-28
Applicant: Micron Technology, Inc.
Inventor： Vincenzo Reina , Christopher Joseph Bueb
IPC: G11C11/406 , G11C5/14 , G11C11/4074 , G11C11/4076
Abstract: Methods, systems, and devices for techniques to refresh memory systems operating in low power states are described. The memory system may operate in a first power mode that includes deactivation of a voltage rail that supplies power to the memory system. The memory system may receive the power over the voltage rail during a time period that the memory system is operating in the first power mode. In some cases, the memory system may determine that the power may be received for a duration and a command is not received during that duration. The memory system may perform a self-refresh operation based on determining that the duration indicated by the timer expires without receiving a command.
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公开(公告)号：US20240220161A1
公开(公告)日：2024-07-04
申请号：US18407086
申请日：2024-01-08
Applicant: Micron Technology, Inc.
Inventor： Christopher Joseph Bueb , Olivier Duval
CPC classification number: G06F3/0659 , G06F3/0613 , G06F3/0664 , G06F3/0673 , G06F9/45558 , G06F2009/45583
Abstract: Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.
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公开(公告)号：US20240160380A1
公开(公告)日：2024-05-16
申请号：US18423002
申请日：2024-01-25
Applicant: Micron Technology, Inc.
Inventor： Olivier Duval , Christopher Joseph Bueb
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.
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公开(公告)号：US11971815B2
公开(公告)日：2024-04-30
申请号：US17463397
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Christopher Joseph Bueb
CPC classification number: G06F12/0246 , G06F3/0619 , G06F3/0644 , G06F3/0656 , G06F3/067 , G06F12/063 , G06F12/0646 , G06F2212/7201 , G06F2212/7211
Abstract: A technique to control write operations in a logical partition. For example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. An accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. In response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. For example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. Write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.
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