公开(公告)号：US10699774B2

公开(公告)日：2020-06-30

申请号：US16189434

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Scott E. Smith

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/22 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

公开(公告)号：US10438649B2

公开(公告)日：2019-10-08

申请号：US15924857

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/50 ,  G11C11/4096 ,  G11C11/4094

Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that couples to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks. The semiconductor device may also include a driver circuit having a pulse generator and a pull-down switch that couples the output buffer to ground, such that the pull-down switch provides the data voltage signal to the output buffer. The semiconductor device may also include a test mode circuit that determines whether the data voltage signal is acceptable and sends an enable signal to the pulse generator in response to the data voltage signal not being acceptable. The enable signal causes the pulse generator to effectively operate with variations in processing, temperature, and voltage properties associated with testing.

公开(公告)号：US20190259440A1

公开(公告)日：2019-08-22

申请号：US15924757

申请日：2018-03-19

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho

IPC: G11C11/4076 ,  G11C7/22 ,  G06F13/16

Abstract: A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.