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    SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES
    22.
    发明申请
    SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20250149108A1

    公开(公告)日：2025-05-08

    申请号：US18775981

    申请日：2024-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Brent Keeth ,  Lance P. Johnson ,  Amy Rae Griffin

    IPC: G11C29/00 ,  G11C29/52

    Abstract: Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.

    DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES
    23.
    发明申请
    DATA PROTECTION TECHNIQUES IN STACKED MEMORY ARCHITECTURES 有权

    公开(公告)号：US20250077353A1

    公开(公告)日：2025-03-06

    申请号：US18762284

    申请日：2024-07-02

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Ameen D. Akel ,  Shivasankar Gunasekaran ,  Sai Krishna Mylavarapu

    IPC: G06F11/10

    Abstract: Methods, systems, and devices for data protection techniques in stacked memory architectures are described. A memory system having a stacked memory architecture may include error correction information associated with a data set that includes multiple data segments stored across multiple memory arrays and, in some examples, multiple dies of the memory system. As part of a write operation for a first data segment of a data set, the memory system may retrieve the remaining data segments of the data set and calculate error correction information using the first data segment and the remaining data segments. As part of a read operation for a second data segment of the data set, the memory system may retrieve each data segment of the data set and perform an error correction operation on the data set using the error correction information.

    ERROR TRACKING BY A MEMORY SYSTEM
    25.
    发明公开
    ERROR TRACKING BY A MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240248781A1

    公开(公告)日：2024-07-25

    申请号：US18391371

    申请日：2023-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu

    IPC: G06F11/07

    CPC classification number: G06F11/0787 ,  G06F11/0727

    Abstract: Methods, systems, and devices for error tracking by a memory system are described. A memory system transmit indications of corrupt data without storing (e.g., internally storing) the indication. In some examples, a memory system may read data (e.g., from an associated memory device) and detect an error in the data. The memory system may generate an indication of the error and may transmit the indication to a host device. In other examples, a host device may transmit corrupted data with an indication of such. The memory system may store the corrupt data (e.g., an inverted version of the corrupt data) and, upon receiving a subsequent read command, may transmit the corrupt data to the host system with an indication that the data is corrupt.

    INVERSION REFRESH OF PHYSICAL MEMORY LOCATION
    26.
    发明申请
    INVERSION REFRESH OF PHYSICAL MEMORY LOCATION 有权

    公开(公告)号：US20220261184A1

    公开(公告)日：2022-08-18

    申请号：US17177802

    申请日：2021-02-17

    Applicant: Micron Technology, Inc.

    Inventor： Sai Krishna Mylavarapu

    IPC: G06F3/06

    Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

    DATA DUPLICATION IN A NON-VOLATILE MEMORY
    27.
    发明申请
    DATA DUPLICATION IN A NON-VOLATILE MEMORY 审中-公开

    公开(公告)号：US20190354429A1

    公开(公告)日：2019-11-21

    申请号：US15983647

    申请日：2018-05-18

    Applicant: Micron Technology, Inc.

    Inventor： Samuel E. Bradshaw ,  Justin Eno ,  Sean Stephen Eilert ,  Sai Krishna Mylavarapu

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.

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