公开(公告)号：US20250147843A1

公开(公告)日：2025-05-08

申请号：US18777165

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Sai Krishna Mylavarapu

IPC: G06F11/10

Abstract: Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.

公开(公告)号：US11579964B2

公开(公告)日：2023-02-14

申请号：US17130885

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC: G06F11/10 ,  G11C11/00 ,  G11C11/4096 ,  G11C11/4074

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US11048580B2

公开(公告)日：2021-06-29

申请号：US16796848

申请日：2020-02-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Justin Eno ,  Sean Stephen Eilert ,  Sai Krishna Mylavarapu

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06

Abstract: Exemplary methods, apparatuses, and systems include a memory controller receiving a user payload to be written to a memory. The memory controller determines a plurality of locations within the memory within which the user payload will be written. After detecting the destination of the user payload, the memory controller detects, within a data structure, the presence of an identifier of a first location within a user data portion of the plurality of locations. The memory controller writes the user payload to the user data portion of the plurality of locations and, in response to detecting the presence of the identifier in the data structure, writes a copy of one or more bits in the user payload written to the first location to a spare data portion of the plurality of locations.

公开(公告)号：US20240403160A1

公开(公告)日：2024-12-05

申请号：US18800272

申请日：2024-08-12

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC: G06F11/10 ,  G11C11/00 ,  G11C11/4074 ,  G11C11/4096

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US11880275B2

公开(公告)日：2024-01-23

申请号：US17889909

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F11/30

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0253

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

公开(公告)号：US20230185660A1

公开(公告)日：2023-06-15

申请号：US18108876

申请日：2023-02-13

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu ,  Todd A. Marquart

IPC: G06F11/10 ,  G11C11/00

CPC classification number: G06F11/1004 ,  G06F11/1068 ,  G11C11/005 ,  G11C11/4096

Abstract: Methods, devices, and systems related to storing parity data in dynamic random access memory (DRAM) are described. In an example, a method can include generating, at a controller, parity data based on user data queued for writing to a non-volatile memory device, receiving the parity data at a DRAM device from the controller and writing the parity data to the DRAM device, receiving the user data at a non-volatile memory device from the controller and writing the user data to the non-volatile memory device, reading the user data from the non-volatile memory device via the controller, and receiving the parity data at the controller from the DRAM device.

公开(公告)号：US20220391284A1

公开(公告)日：2022-12-08

申请号：US17889909

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F11/10 ,  G06F11/07 ,  G06F12/02 ,  G06F11/30

Abstract: Various embodiments described herein provide for copying (e.g., to cache) a portion of defect management data for a block of a memory device, such as a non-volatile memory device of a memory sub-system, based on activity of the memory device. For instance, the portion of defect management data can be copied from a first-type memory device of the memory sub-system to a second-type memory device of the memory sub-system, where the first-type memory device stores defect management data for a working set of blocks of the non-volatile memory device being operated upon by the memory sub-system, where the second-type memory device is used to store defect management data for an active block of the working set of blocks, and where the second-type memory device has a faster access (e.g., read or write access) than the first-type memory device.

公开(公告)号：US11037637B2

公开(公告)日：2021-06-15

申请号：US16215267

申请日：2018-12-10

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44 ,  G11C29/04

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device performs an error recovery flow (ERF) to recover a unit of data comprising data and a write timestamp indicating when the unit of data was written. The processing device determines whether to perform a defect detection operation to detect a defect in the memory component using a bit error rate (BER), corresponding to the read operation, and the write timestamp in the unit of data. The processing device initiates the defect detection operation responsive to the BER condition not being expected for the calculated W2R (based on the write timestamp). The processing device can use an ERF condition and the write timestamp to determine whether to perform the defect detection operation. The processing device initiates the defect detection operation responsive to the ERF condition not being expected the calculated W2R (based on the write timestamp).

公开(公告)号：US20240264904A1

公开(公告)日：2024-08-08

申请号：US18421444

申请日：2024-01-24

Applicant: Micron Technology, Inc.

Inventor： Sai Krishna Mylavarapu

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/14

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1435

Abstract: Methods, systems, and devices for logical counters for a memory system are described. A controller within a memory system may generate one or more logical counters that each correspond to a management counter of a memory die. The controller may store the logical counters at a logical address space associated with the memory system. The logical address space may correspond to a physical location within a memory array of the memory die. The controller may periodically read a value of a management counter and store the value to the logical counter. In some examples, if the memory system detects an error condition for the management counter, the memory system may perform a recovery operation for the data stored at the memory die.

公开(公告)号：US11688467B2

公开(公告)日：2023-06-27

申请号：US17347570

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sai Krishna Mylavarapu ,  Zhenlei Shen ,  Tingjun Xie ,  Charles S. Kwong

IPC: G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G11C16/26 ,  G11C29/42 ,  G06F11/07 ,  G06F11/14 ,  G11C29/44 ,  G11C29/04

CPC classification number: G11C16/3404 ,  G06F11/076 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/141 ,  G11C16/26 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G06F2201/81 ,  G11C2029/0411

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.