公开(公告)号：US11749331B2

公开(公告)日：2023-09-05

申请号：US17662733

申请日：2022-05-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Wu ,  Yu Zhang ,  Dong Pan

IPC: G11C11/401 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/402

CPC classification number: G11C11/40611 ,  G11C11/402 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G11C11/40618

Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

公开(公告)号：US11688451B2

公开(公告)日：2023-06-27

申请号：US17456849

申请日：2021-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu Zhang ,  Liang Li

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: Apparatuses, systems, and methods for main sketch and slim sketch circuits for address tracking. The main sketch circuit receives a row address and changes selected count values in a first storage structure based on hash values generated based on the row address. Those count values are compared to a first threshold, and if that threshold is exceeded, a slim sketch circuit also receives the row address and changes selected count values in a second storage structure based on hash values generated based on the row address. Based on the selected count values from the first storage structure, the second storage structure, or combinations thereof, the row address may be determined to be an aggressor address.

公开(公告)号：US20220247430A1

公开(公告)日：2022-08-04

申请号：US17723277

申请日：2022-04-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Bing Shang ,  Yu Zhang ,  Hong Wen Li ,  Yu Peng Fan ,  Zhong Lai Liu ,  En Peng Gao ,  Liang Zhang

IPC: H03M13/45 ,  G06F9/38 ,  G06F11/10 ,  H03M13/00

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

公开(公告)号：US11348631B2

公开(公告)日：2022-05-31

申请号：US16997659

申请日：2020-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Wu ,  Yu Zhang ,  Dong Pan

IPC: G11C11/402 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408

Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

公开(公告)号：US20220068429A1

公开(公告)日：2022-03-03

申请号：US17483009

申请日：2021-09-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Bin Du ,  Liang Li ,  Yu Zhang ,  Yin Lu

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/10 ,  G11C29/02 ,  G11C29/12

Abstract: Embodiments of the disclosure are drawn to apparatuses methods for checking redundancy information for row addresses prior to performing various refresh operations, such as auto refresh and targeted refresh operations. In some examples, refresh operations may be multi pump refresh operations. In some examples, a targeted refresh operation may be performed prior to an auto refresh operation responsive to a multi pump refresh operation. In some examples, redundancy information for the auto refresh operation may be performed, at least in part, during the targeted refresh operation. In some examples, refresh operations on word lines may be skipped when the redundancy information indicates the word line is defective or unused.

公开(公告)号：US10860470B2

公开(公告)日：2020-12-08

申请号：US16540654

申请日：2019-08-14

Applicant: Micron Technology, Inc.

Inventor： Yu Zhang ,  Jun Wu ,  Yuan He

IPC: G06F12/00 ,  G11C15/04 ,  H03K19/1776 ,  H03K19/20 ,  G11C11/408 ,  G11C11/406 ,  G06F13/00 ,  G06F13/28

Abstract: A method of operating a memory device may include receiving, during a phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content-addressable memory (CAM). The method further includes storing, during the phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Further, the method includes refreshing the stored RHA of the CAM via a RHR during the RHR interval.

公开(公告)号：US20230170008A1

公开(公告)日：2023-06-01

申请号：US17456849

申请日：2021-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu Zhang ,  Liang Li

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: Apparatuses, systems, and methods for main sketch and slim sketch circuits for address tracking. The main sketch circuit receives a row address and changes selected count values in a first storage structure based on hash values generated based on the row address. Those count values are compared to a first threshold, and if that threshold is exceeded, a slim sketch circuit also receives the row address and changes selected count values in a second storage structure based on hash values generated based on the row address. Based on the selected count values from the first storage structure, the second storage structure, or combinations thereof, the row address may be determined to be an aggressor address.

公开(公告)号：US11309919B2

公开(公告)日：2022-04-19

申请号：US16593479

申请日：2019-10-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wei Bing Shang ,  Yu Zhang ,  Hong Wen Li ,  Yu Peng Fan ,  Zhong Lai Liu ,  En Peng Gao ,  Liang Zhang

IPC: H03M13/45 ,  H03M13/00 ,  G06F11/10 ,  G06F11/00 ,  G06F9/38

Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.

公开(公告)号：US20220059153A1

公开(公告)日：2022-02-24

申请号：US16997766

申请日：2020-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu Zhang ,  Liang Li ,  Jun Wu

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.

公开(公告)号：US20200090749A1

公开(公告)日：2020-03-19

申请号：US16135877

申请日：2018-09-19

Applicant: Micron Technology, Inc.

Inventor： Yu Zhang ,  Jun Wu ,  Yuan He

IPC: G11C15/04 ,  H03K19/177 ,  H03K19/20

Abstract: A method of operating a memory device may include receiving, during each phase of a row hammer refresh (RHR) interval, at least one row hammer address (RHA) of a content addressable memory (CAM). The method may further include storing, during each phase of the RHR interval, a received RHA of the at least one received RHA in an address register. Moreover, the method may include refreshing each stored RHA of the CAM via a RHR during the RHR interval. Semiconductor devices and an electronic system are also described.