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公开(公告)号：US20200036396A1
公开(公告)日：2020-01-30
申请号：US16593479
申请日：2019-10-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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2.发明申请APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING 审中-公开用于管理具有错误校正编码的存储器操作的装置和方法公开(公告)号：US20160315639A1
公开(公告)日：2016-10-27
申请号：US14423343
申请日：2014-12-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
Abstract translation: 公开了用于通过纠错编码流水线存储器操作的装置和方法。 公开了一种用于流水线连续写入掩模操作的方法，其中在第一写入掩码操作的纠错码计算期间发生第二写入掩模操作的第二读取操作。 该方法还可以包括在第二写入掩码操作的纠错码计算期间从第一写入掩码操作中写入数据。 公开了一种用于流水线连续操作的方法，其中如果第一操作不是写掩码操作，则可以取消第一读取操作。 公开了一种包括具有单独的全局读和写输入 - 输出线的存储器的装置。
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公开(公告)号：US11955991B2
公开(公告)日：2024-04-09
申请号：US17723277
申请日：2022-04-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
CPC classification number: H03M13/45 , G06F9/38 , G06F11/1048 , H03M13/611
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US20220247430A1
公开(公告)日：2022-08-04
申请号：US17723277
申请日：2022-04-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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Patent Agency Ranking
公开(公告)号：US10447316B2
公开(公告)日：2019-10-15
申请号：US14423343
申请日：2014-12-19
Applicant: Micron Technology, Inc.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US09148176B2
公开(公告)日：2015-09-29
申请号：US14002092
申请日：2013-06-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu Zhang , Wei Bing Shang , En Peng Gao
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G11C29/42 , G11C2029/0411 , H03M13/2942 , H03M13/6561
Abstract: One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.
Abstract translation: 一个示例性设备包括：第一电路，被配置为接收第一和第二数据字，以校正第一数据字中的一个或多个错误，以响应于控制信号合并校正的第一数据字和第二数据字，以产生最终合并 数据字，并将最终合并的数据字提供给写入电路。 该装置还包括配置为还接收第一和第二数据字的第二电路，以响应于控制信号预先合并第一和第二数据字以产生初始合并数据字，以产生用于初始合并的初始奇偶校验码 数据字，以校正初始奇偶校验码，并将校正的奇偶校验码提供给写电路。
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公开(公告)号：US11309919B2
公开(公告)日：2022-04-19
申请号：US16593479
申请日：2019-10-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Wei Bing Shang , Yu Zhang , Hong Wen Li , Yu Peng Fan , Zhong Lai Liu , En Peng Gao , Liang Zhang
Abstract: Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed.
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公开(公告)号：US09703633B2
公开(公告)日：2017-07-11
申请号：US14848045
申请日：2015-09-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yu Zhang , Wei Bing Shang , En Peng Gao
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G11C29/42 , G11C2029/0411 , H03M13/2942 , H03M13/6561
Abstract: One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarily merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.
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公开(公告)号：US20150378826A1
公开(公告)日：2015-12-31
申请号：US14848045
申请日：2015-09-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： YU ZHANG , Wei Bing Shang , En Peng Gao
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1048 , G11C29/42 , G11C2029/0411 , H03M13/2942 , H03M13/6561
Abstract: One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarliy merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit.
Abstract translation: 一个示例性设备包括：第一电路，被配置为接收第一和第二数据字，以校正第一数据字中的一个或多个错误，以响应于控制信号合并校正的第一数据字和第二数据字，以产生最终合并 数据字，并将最终合并的数据字提供给写入电路。 该装置还包括配置为还接收第一和第二数据字的第二电路，以响应于控制信号预先合并第一和第二数据字以产生初始合并数据字，以产生用于初始合并的初始奇偶校验码 数据字，以校正初始奇偶校验码，并将校正的奇偶校验码提供给写电路。
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