公开(公告)号：US06732252B2

公开(公告)日：2004-05-04

申请号：US10195975

申请日：2002-07-16

申请人： Yoichiro Miki ,  Masahiro Tani ,  Kazuki Ninomiya ,  Naoya Tokunaga ,  Kenta Sokawa ,  Hiroshi Miyaguchi ,  Yuji Yaguchi ,  Tsuyoshi Akiyama ,  Kenya Adachi

发明人： Yoichiro Miki ,  Masahiro Tani ,  Kazuki Ninomiya ,  Naoya Tokunaga ,  Kenta Sokawa ,  Hiroshi Miyaguchi ,  Yuji Yaguchi ,  Tsuyoshi Akiyama ,  Kenya Adachi

IPC分类号： G06F1200

CPC分类号： G06F9/345 ,  G06F13/1673 ,  H04N19/423 ,  H04N19/61

摘要： A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

摘要翻译： 本发明的存储器接口装置包括：输入缓冲器，包括多个输入区域; 包括多个输出区域的输出缓冲器; 以及用于控制输入缓冲器，输出缓冲器和单端口存储器的控制部分。 控制部分控制输入缓冲器和单端口存储器，以将存储在输入缓冲器的一个输入区域中的信号传送到单端口存储器，同时将输入信号存储在输入缓冲器的另一个输入区域中 。 控制部分控制输出缓冲器和单端口存储器，以将存储在单端口存储器中的信号传送到输出区域中的另一个输出端，从而作为输出信号输出存储在输出缓冲器的一个输出区域中的信号 的输出缓冲区。

公开(公告)号：US6128733A

公开(公告)日：2000-10-03

申请号：US165574

申请日：1998-10-02

申请人： Hiroshi Miyaguchi ,  Naoya Tokunaga

发明人： Hiroshi Miyaguchi ,  Naoya Tokunaga

IPC分类号： G06F9/06 ,  G06F9/445 ,  G06F15/177

CPC分类号： G06F9/445

摘要： A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system. In the ROM 10, multiple address pointers are stored in specified storage areas, and corresponding sets of program data are stored in the storage locations indicated by the address pointers in such a manner that a first set of program data is stored in the specified storage area which utilizes the address corresponding to the first address pointer as the start storage address, and a second set of program data is stored in the specified storage area which utilizes the address corresponding to the second address pointer as the start storage address.

摘要翻译： 一种用于以高速度和高效率加载程序数据的方法，即使存储在程序存储器中的程序数据的存储地址和数据长度发生变化也不需要软件修改。 为了将程序数据以可重写的方式加载到多个功能电路FC0，FC1，...中。 。 。 ，根据提供的程序数据操作的FCn，在系统中提供程序存储器，例如ROM 10，程序加载器12和程序指定装置，例如微处理器14。 在ROM10中，多个地址指针被存储在指定的存储区域中，并且相应的程序数据组被存储在由地址指针指示的存储位置中，使得第一组程序数据被存储在指定的存储区域 其利用与第一地址指针相对应的地址作为开始存储地址，并且将第二组程序数据存储在利用与第二地址指针相对应的地址作为起始存储地址的指定存储区域中。

公开(公告)号：US6047366A

公开(公告)日：2000-04-04

申请号：US993803

申请日：1997-12-18

申请人： Kazuhiro Ohara ,  Hiroshi Miyaguchi ,  Yuji Yaguchi

发明人： Kazuhiro Ohara ,  Hiroshi Miyaguchi ,  Yuji Yaguchi

IPC分类号： G06F15/80 ,  G06F15/76

CPC分类号： G06F15/8015

摘要： A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

摘要翻译： 单指令多数据（SIMD）处理器（10），其包含用于视频数据的水平缩放的特征。 处理器（10）具有数据输入寄存器（11），其可操作以将输入数据字存储在数据输入寄存器（11）中的顺序位置，并将输入数据字传送到处理元件阵列。 处理器（10）还具有输出数据寄存器（16），其可操作以从处理元件阵列接收数据输出字，并从所述输出数据阵列的顺序位置输出所述数据输出字。 输入到处理器的输入跳过信号导致顺序数据写入操作跳过输入数据寄存器的位置，而到处理器的输出跳过信号导致顺序数据读取操作跳过输出数据寄存器的位置。

公开(公告)号：US5093722A

公开(公告)日：1992-03-03

申请号：US486662

申请日：1990-03-01

申请人： Hiroshi Miyaguchi ,  Jimmie D. Childers

发明人： Hiroshi Miyaguchi ,  Jimmie D. Childers

IPC分类号： H04N5/14 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N5/46 ,  H04N7/01 ,  H04N7/015 ,  H04N9/64 ,  H04N9/77 ,  H04N9/78 ,  H04N11/04 ,  H04N11/20

CPC分类号： H04N5/4448 ,  H04N5/144 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N7/012 ,  H04N9/646 ,  H04N9/78

摘要： A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system.

公开(公告)号：US5091783A

公开(公告)日：1992-02-25

申请号：US486663

申请日：1990-03-01

申请人： Hiroshi Miyaguchi

发明人： Hiroshi Miyaguchi

IPC分类号： H04N5/14 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N9/64 ,  H04N9/78

CPC分类号： H04N5/4448 ,  H04N5/144 ,  H04N5/208 ,  H04N5/44 ,  H04N5/45 ,  H04N7/012 ,  H04N9/646 ,  H04N9/78

摘要： A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suitable for television processing. The processor receives data samples fo each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a still picture may be displayed.

摘要翻译： 电视接收系统包括具有至少一个单指令多数据处理器的数字单元，特别适用于电视处理。 处理器连续地接收每个水平行字的数据样本，但并行处理该行。 处理器具有并发操作的输入，计算和输出层。 内部寄存器文件模拟行存储器，以消除对外部线路存储器的需要。 处理器可以用从主机开发系统下载到其中的各种改进的定义电视任务进行编程。 场存储器和多路复用器控制数据流，从而可以显示静止图像。

公开(公告)号：US4510578A

公开(公告)日：1985-04-09

申请号：US352236

申请日：1982-02-25

申请人： Hiroshi Miyaguchi ,  Hisaharu Takeuchi

发明人： Hiroshi Miyaguchi ,  Hisaharu Takeuchi

IPC分类号： G06F7/548 ,  G06F17/16 ,  H04N11/04 ,  G06F15/332

CPC分类号： H04N11/044

摘要： The invention provides an encoder for subjecting an input signal to the orthogonal transform for band compression and encoding. The encoder has a sample and hold circuit which samples the input signal at a sampling frequency three times that of the input signal, and an orthogonal transform unit which subjects the sampled signal to the orthogonal transform using as a coefficient an orthogonal matrix function of the order of 3n (where n is an integer of 2 or more) having as a minor matrix an orthogonal matrix of the order of 3: ##EQU1## having given numbers a, b and c as matrix elements. By maintaining the sampling frequency low, the frequency components of the input signal may be concentrated in a small number of transform outputs without causing an increase in the amount of data to be processed, without using a multiplier and without requiring an increase in the processing speed. The input signal is thus effectively band compressed and encoded.

摘要翻译： 本发明提供一种用于对输入信号进行正交变换以进行频带压缩和编码的编码器。 编码器具有采样保持电路，其采样频率为输入信号三倍的采样频率，以及正交变换单元，其使采样信号进行正交变换，作为系数的顺序正交矩阵函数 具有作为次要矩阵的3n（其中n是2或更大的整数）具有给定数量a，b和c作为矩阵元素的3：3的正交矩阵。 通过保持采样频率较低，输入信号的频率分量可以集中在少量的变换输出中，而不会导致要处理的数据量的增加，而不需要使用乘法器，而不需要增加处理速度 。 因此，输入信号被有效地进行频带压缩和编码。