公开(公告)号：US20220093510A1

公开(公告)日：2022-03-24

申请号：US17031073

申请日：2020-09-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/528 ,  H01L27/108 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure relates to a semiconductor device including a conductive contact having a tapering profile and a method for preparing the semiconductor device. The semiconductor device includes a conductive layer disposed over a semiconductor substrate, and a conductive contact disposed over the conductive layer. The semiconductor device also includes a conductive line disposed over the conductive contact. An upper portion of the conductive contact has a tapering profile in a first cross-sectional view along a longitudinal axis of the conductive line, and the upper portion of the conductive contact has a non-tapering profile in a second cross-sectional view along a line orthogonal to the longitudinal axis of the conductive line.

公开(公告)号：US20220028776A1

公开(公告)日：2022-01-27

申请号：US16934833

申请日：2020-07-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/498 ,  H01L23/528 ,  H01L21/48 ,  H01L23/00

摘要： The present application discloses a semiconductor device with two stress-relieving structures and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a first stress-relieving structure including a first conductive frame positioned above the semiconductor substrate and a plurality of first insulating pillars positioned within the conductive frame, a second stress-relieving structure including a plurality of second conductive pillars positioned above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars is positioned within the second insulating frame, and a conductive structure including a supporting portion positioned above the second stress-relieving structure, a conductive portion positioned adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion. The plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame.

公开(公告)号：US20210375803A1

公开(公告)日：2021-12-02

申请号：US16885939

申请日：2020-05-28

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/00

摘要： The present disclosure discloses a semiconductor device structure with an air gap for reducing capacitive coupling and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive pad over a first semiconductor substrate, and a first conductive structure over the first conductive pad. The semiconductor device structure also includes a second conductive structure over the first conductive structure, and a second conductive pad over the second conductive structure. The second conductive pad is electrically connected to the first conductive pad through the first and the second conductive structures. The semiconductor device structure further includes a second semiconductor substrate over the second conductive pad, a first passivation layer between the first and the second semiconductor substrates and covering the first conductive structure, and a second passivation layer between the first passivation layer and the second semiconductor substrate. The first and the second passivation layers surround the second conductive structure, and a first air gap is enclosed by the first and the second passivation layers.

公开(公告)号：US20210305182A1

公开(公告)日：2021-09-30

申请号：US16829698

申请日：2020-03-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer. The alleviation structure includes a first connecting interlayer respectively electrically coupled to the plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and a plurality of alleviation structures positioned between the plurality of first conductive features in the first insulating layer and the plurality of first conductive features in the second insulating layer, wherein a porosity of the plurality of alleviation structures is between about 25% and about 100%.

公开(公告)号：US20210249355A1

公开(公告)日：2021-08-12

申请号：US16789091

申请日：2020-02-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/532 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

摘要： The present application discloses a semiconductor device with a graded porous dielectric structure. The semiconductor device includes a substrate; two conductive features positioned apart from each other over the substrate; a graded porous dielectric structure positioned between the two conductive features; and a dielectric layer positioned between one of the two conductive features and the graded porous dielectric structure; wherein the graded porous dielectric structure comprises a first portion having a first porosity and a second portion having a second porosity, and the second porosity is higher than the first porosity.

公开(公告)号：US20210118830A1

公开(公告)日：2021-04-22

申请号：US16656823

申请日：2019-10-18

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L23/00

摘要： The present application provides a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate, and a first spacer disposed over a sidewall of the bonding pad. The semiconductor device also includes a first passivation layer covering the bonding pad and the first spacer, and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain region in the semiconductor substrate through the bonding pad.

公开(公告)号：US20210098461A1

公开(公告)日：2021-04-01

申请号：US16583288

申请日：2019-09-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shing-Yih SHIH ,  Tse-Yao HUANG

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L23/528

摘要： A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region.

公开(公告)号：US20210074804A1

公开(公告)日：2021-03-11

申请号：US16561513

申请日：2019-09-05

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L49/02 ,  H01L23/528 ,  H01L21/02 ,  C23C16/40

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a conductive feature comprising tungsten positioned above the substrate, a coverage layer comprising tungsten nitride positioned on a top surface of the conductive feature, and a plurality of capacitor structures positioned above the substrate.

公开(公告)号：US20230371232A1

公开(公告)日：2023-11-16

申请号：US17741837

申请日：2022-05-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897

摘要： A method for forming a memory device includes: forming an array of memory cells, wherein the memory cells respectively include an access transistor embedded in a semiconductor substrate and a storage capacitor over the semiconductor substrate and coupled to the access transistor; and forming a peripheral circuit around the memory cells, wherein the peripheral circuit includes a first transistor and a second transistor on the semiconductor substrate and each including a protruding channel structure and a gate structure covering the protruding channel structure, the protruding channel structure has a bottom part and an upper part, and the upper part has a top width and a bottom width smaller the top width

公开(公告)号：US20230062967A1

公开(公告)日：2023-03-02

申请号：US17462309

申请日：2021-08-31

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao HUANG

IPC分类号： H01L21/74 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/485

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a dense area and an open area; a dielectric structure positioned on the substrate; a landing pad positioned in the dielectric structure and above the dense area; a first contact positioned on the landing pad and in the dielectric structure; and a second contact positioned in the dielectric structure and on the open area of the substrate. A top surface of the first contact and a top surface of the second contact are substantially coplanar. A width of the first contact is less than the one half of a width of the second contact.