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21.发明授权公开(公告)号：US10673391B2
公开(公告)日：2020-06-02
申请号：US16402349
申请日：2019-05-03
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US10326411B2
公开(公告)日：2019-06-18
申请号：US15802617
申请日：2017-11-03
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US10163416B2
公开(公告)日：2018-12-25
申请号：US14801855
申请日：2015-07-17
Applicant: Novatek Microelectronics Corp.
Inventor： Chieh-An Lin , Jhih-Siou Cheng , Po-Hsiang Fang , Po-Yu Tseng , Ju-Lin Huang , Yi-Chuan Liu
IPC: G09G3/36
Abstract: A display apparatus and a driving method of the same are provided. The display apparatus includes a display panel, a gate driver circuit, and a source driver circuit. During a functional sub-period of a frame period, the gate driver circuit simultaneously drives a plurality of gate lines, and the source driver circuit drives a plurality of source lines, so as to perform a function on a plurality of pixels connected to the gate lines. In a scan sub-period of the frame period, the gate driver circuit drives the gate lines according to a scan sequence, and the source driver circuit correspondingly drives the source lines according to the scan sequence of the gate driver circuit in the first scan sub-period, so as to display an image.
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24.发明申请公开(公告)号：US20180337642A1
公开(公告)日：2018-11-22
申请号：US15802617
申请日：2017-11-03
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
CPC classification number: H03F1/3205 , H03F1/086 , H03F1/301 , H03F1/3211 , H03F1/523 , H03F3/45183 , H03F3/4521 , H03F3/45219 , H03F3/45237 , H03F3/45381 , H03F3/45632 , H03F2203/45342 , H03F2203/45352 , H03F2203/45382 , H03F2203/45384 , H03K17/063 , H03K17/0822
Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US09842528B2
公开(公告)日：2017-12-12
申请号：US15256753
申请日：2016-09-06
Applicant: Novatek Microelectronics Corp.
Inventor： Po-Yu Tseng , Jhih-Siou Cheng , Pang-Chen Hung
IPC: G09G3/3275 , G09G3/20
CPC classification number: G09G3/20 , G09G2310/027 , G09G2310/0289 , G09G2330/025 , G09G2330/045
Abstract: A driving device is provided. The driving device includes a first code mapping circuit, a first source driving channel, a second code mapping circuit and a second source driving channel. The first code mapping circuit converts a first input code in input data into a first intermediate code according to a first code-to-code mapping relation. The first source driving channel converts the first intermediate code into a first analog voltage according to a first code-to-voltage mapping relation. The second code mapping circuit converts a second input code in the input data into a second intennediate code according to a second code-to-code mapping relation which is different from the first code-to-code mapping relation. The second source driving channel converts the second intermediate code into a second analog voltage according to a second code-to-voltage mapping relation which is different from the first code-to-voltage mapping relation.
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Patent Agency Ranking
公开(公告)号：US09536462B2
公开(公告)日：2017-01-03
申请号：US14534167
申请日：2014-11-06
Applicant: Novatek Microelectronics Corp.
Inventor： Po-Yu Tseng , Jhih-Siou Cheng , Pang-Chen Hung
IPC: G09G3/3275 , G09G3/20
CPC classification number: G09G3/20 , G09G2310/0264 , G09G2310/027 , G09G2310/0289 , G09G2330/025 , G09G2330/045
Abstract: A driving device and a source driving method are provided. The driving device includes a first code mapping unit, a first source driving channel, a second code mapping unit and a second source driving channel. The first code mapping unit converts a first input code in input data into a first intermediate code according to a first code-to-code mapping relation. The first source driving channel converts the first intermediate code into a first analog voltage according to a first code-to-voltage mapping relation. The second code mapping unit converts a second input code in the input data into a second intermediate code according to a second code-to-code mapping relation which is different from the first code-to-code mapping relation. The second source driving channel converts the second intermediate code into a second analog voltage according to a second code-to-voltage mapping relation which is different from the first code-to-voltage mapping relation.
Abstract translation: 提供驱动装置和源驱动方法。 驱动装置包括第一码映射单元，第一源驱动信道，第二码映射单元和第二源驱动信道。 第一代码映射单元根据第一代码映射关系将输入数据中的第一输入代码转换为第一中间代码。 第一源驱动通道根据第一代码电压映射关系将第一中间代码转换成第一模拟电压。 第二代码映射单元根据与第一代码到代码映射关系不同的第二代码到代码映射关系将输入数据中的第二输入代码转换为第二中间代码。 第二源极驱动通道根据与第一代码电压映射关系不同的第二代码到电压映射关系将第二中间代码转换成第二模拟电压。
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公开(公告)号：US09396695B2
公开(公告)日：2016-07-19
申请号：US14561200
申请日：2014-12-04
Applicant: Novatek Microelectronics Corp.
Inventor： Jr-Ching Lin , Hsin-Hung Lee , Chia-Wei Su , Po-Yu Tseng , Shun-Hsun Yang , Po-Hsiang Fang
CPC classification number: G09G3/3696 , G09G1/005 , G09G3/3688 , G09G2320/0673
Abstract: A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data and a first reference voltage group, for driving the display device. The voltage controller receives a voltage command during a line data transmitting period, a horizontal blanking period or a vertical blanking period for generating a first reference voltage configuration data. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data for applying the first reference voltage group to the first drive channel circuit. Furthermore, a method for driving a display device is also provided.
Abstract translation: 源驱动器包括第一驱动通道电路，电压控制器和第一可编程电压缓冲器单元。 第一驱动通道电路接收第一像素数据和第一参考电压组，用于驱动显示装置。 电压控制器在行数据发送期间，水平消隐期间或垂直消隐期间接收电压指令，以产生第一参考电压配置数据。 第一可编程电压缓冲器单元耦合到电压控制器和第一驱动通道电路，并且接收用于将第一参考电压组施加到第一驱动通道电路的第一参考电压配置数据。 此外，还提供了一种用于驱动显示装置的方法。
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公开(公告)号：US09123275B2
公开(公告)日：2015-09-01
申请号：US13778122
申请日：2013-02-27
Applicant: Novatek Microelectronics Corp.
Inventor： Shun-Hsun Yang , Chia-Wei Su , Po-Yu Tseng , Po-Hsiang Fang , Hsin-Hung Lee
CPC classification number: G09G3/006 , G09G3/3688 , G09G2330/12 , G09G2370/08
Abstract: A method for displaying error rates of data channels of a display is provided. A timing controller of the display repeatedly transmits a test signal with a specific format to a first and a second source drivers of the display via a first and a second data channels of the display. During testing, a first number and a second number of times of the first source driver and the second source driver determining that the received test signal does not have the specific format are counted respectively. The first and the second source drivers control displaying of a first area and a second area of a panel of the display respectively according to the counted first and second numbers of times. Accordingly, the error rates of the data channels are presented on the panel of the display in a way that the error rates could be recognized more easily.
Abstract translation: 提供了一种用于显示显示器的数据通道的错误率的方法。 显示器的定时控制器经由显示器的第一和第二数据通道重复地将特定格式的测试信号发送到显示器的第一和第二源驱动器。 在测试期间，分别计数第一源驱动器和第二源驱动器的第一次数和第二次数，以确定所接收的测试信号不具有特定格式。 第一和第二源驱动器分别根据计数的第一和第二次数来分别显示显示器的面板的第一区域和第二区域。 因此，数据通道的错误率以更容易识别错误率的方式呈现在显示器的面板上。
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公开(公告)号：US08947408B2
公开(公告)日：2015-02-03
申请号：US13677314
申请日：2012-11-15
Applicant: Novatek Microelectronics Corp.
Inventor： Jr-Ching Lin , Hsin-Hung Lee , Chia-Wei Su , Po-Yu Tseng , Shun-Hsun Yang , Po-Hsiang Fang
CPC classification number: G09G3/3696 , G09G1/005 , G09G3/3688 , G09G2320/0673
Abstract: A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data from the timing controller via a data bus, converts the first pixel data to a first drive voltage according to a first reference voltage group, and drives a display panel by the first drive voltage. The voltage controller receives a voltage command from the timing controller, generates and changes a first reference voltage configuration data according to the voltage command. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data to generate and adjust the first reference voltage group for applying to the first drive channel circuit. Furthermore, a method for updating a new gamma curve by the source driver is also provided.
Abstract translation: 源驱动器包括第一驱动通道电路，电压控制器和第一可编程电压缓冲器单元。 第一驱动通道电路经由数据总线从定时控制器接收第一像素数据，根据第一参考电压组将第一像素数据转换为第一驱动电压，并且通过第一驱动电压驱动显示面板。 电压控制器从定时控制器接收电压指令，根据电压指令产生并改变第一参考电压配置数据。 第一可编程电压缓冲器单元耦合到电压控制器和第一驱动通道电路，并且接收第一参考电压配置数据以产生和调整第一参考电压组以施加到第一驱动通道电路。 此外，还提供了用于由源驱动器更新新伽玛曲线的方法。
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公开(公告)号：US20130266030A1
公开(公告)日：2013-10-10
申请号：US13684576
申请日：2012-11-26
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor： Chia-Wei Su , Shun-Hsun Yang , Hsin-Hung Lee , Po-Hsiang Fang , Po-Yu Tseng , Li-Tang Lin
IPC: H04J3/00
CPC classification number: H04J3/00 , H04J3/0658
Abstract: A data transmission device includes a data division unit for receiving an original transmission data and dividing the original transmission data into a plurality of division data; a data generation unit for generating a plurality of packet data according to the plurality of division data and a plurality of clock data, wherein each of the clock data is a multi-bit data; and a data output unit for outputting the plurality of packet data to a data reception device; where each of the packet data includes a division data and a clock data, each of the packet data corresponds to a packet data period, and the division data corresponds to a division data period of the packet data period and the clock data corresponds to a clock period of the packet data period.
Abstract translation: 数据传输装置包括：数据分割单元，用于接收原始发送数据，并将原始发送数据划分成多个分割数据; 数据生成单元，用于根据多个分割数据生成多个分组数据和多个时钟数据，其中每个时钟数据是多位数据; 以及数据输出单元，用于将数据分组数据输出到数据接收装置; 其中每个分组数据包括分割数据和时钟数据，每个分组数据对应于分组数据周期，并且分割数据对应于分组数据周期的分割数据周期，并且时钟数据对应于时钟 分组数据周期。
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