公开(公告)号：US20230297499A1

公开(公告)日：2023-09-21

申请号：US17581687

申请日：2022-01-21

Applicant: NVIDIA Corporation

Inventor： William James Dally ,  Stephen William Keckler ,  Carl Thomas Gray ,  James Michael O’Connor

IPC: G06F12/02

CPC classification number: G06F12/0238 ,  G06F2212/657

Abstract: A mapper within a single-level memory system may facilitate memory localization to reduce the energy and latency of memory accesses within the single-level memory system. The mapper may translate a memory request received from a processor for implementation at a data storage entity, where the translating identifies a data storage entity and a starting location within the data storage entity where the data associated with the memory request is located. This data storage entity may be co-located with the processor that sent the request, which may enable the localization of memory and significantly improve the performance of memory usage by reducing an energy of data access and increasing data bandwidth.

公开(公告)号：US20210242837A1

公开(公告)日：2021-08-05

申请号：US16778895

申请日：2020-01-31

Applicant: Nvidia Corporation

Inventor： Sanquan Song ,  John Poulton ,  Carl Thomas Gray

IPC: H03F1/08 ,  H03F1/26

Abstract: The disclosure provides an improved transimpedance amplifier (TIA) that can operate at a higher bandwidth and lower noise compared to conventional TIAs. The TIA employs a data path with both feedback impedance and feedback capacitance for improved performance. The feedback impedance includes at least two resistors in series and at least one shunt capacitor, coupled between the at least two resistors, that helps to extend the circuit bandwidth and improve SNR at the same time. The capacitance value of the shunt capacitor can be selected based on both the bandwidth and noise. In one example, the TIA includes: (1) a biasing path, and (2) a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. An optical receiver and a circuit having the TIA are also disclosed.

公开(公告)号：US10224813B2

公开(公告)日：2019-03-05

申请号：US15080461

申请日：2016-03-24

Applicant: NVIDIA Corporation

Inventor： Sudhir Shrikantha Kudva ,  William J. Dally ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H02M3/157 ,  H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: A system and method are provided for controlling a modified buck converter circuit. A pull-up switching mechanism that is coupled to an upstream terminal of an inductor within a modified buck converter circuit is enabled. A load current at the output of the modified buck regulator circuit is measured. A capacitor current associated with a capacitor that is coupled to a downstream terminal of the inductor is continuously sensed and the pull-up switching mechanism is disabled when the capacitor current is greater than a sum of the load current and an enabling current value.

公开(公告)号：US09171607B2

公开(公告)日：2015-10-27

申请号：US13938161

申请日：2013-07-09

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Brucek Kurdo Khailany ,  Carl Thomas Gray

IPC: G11C11/40 ,  G11C11/4096 ,  G11C7/10 ,  H04L25/02

CPC classification number: G11C11/4096 ,  G11C7/1057 ,  G11C7/1069 ,  H04L25/0276

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，系统功能芯片和被配置为包括第一处理器芯片和系统功能芯片的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 系统功能芯片被配置为包括第二GRS接口电路。 在MCM封装内制造第一组电迹线，并耦合到第一GRS接口电路和第二GRS接口电路。 第一GRS接口电路和第二GRS接口电路一起提供第一处理器芯片和系统功能芯片之间的通信通道。