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    Signaling over RC-dominated transmission lines
    1.
    发明授权
    Signaling over RC-dominated transmission lines 有权

    公开(公告)号：US12237878B2

    公开(公告)日：2025-02-25

    申请号：US18086351

    申请日：2022-12-21

    Applicant: NVIDIA Corporation

    Inventor： John Poulton ,  Sanquan Song ,  Xi Chen ,  Walker Turner ,  Yoshinori Nishi ,  John M. Wilson

    IPC: H04B3/04

    Abstract: The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

    Transimpedance amplifier for converting electrical currents to voltages
    4.
    发明授权
    Transimpedance amplifier for converting electrical currents to voltages 有权

    公开(公告)号：US11165394B2

    公开(公告)日：2021-11-02

    申请号：US16778895

    申请日：2020-01-31

    Applicant: Nvidia Corporation

    Inventor： Sanquan Song ,  John Poulton ,  Carl Thomas Gray

    IPC: H03F3/08 ,  H03F1/08 ,  H03F1/26

    Abstract: The disclosure provides an improved transimpedance amplifier (TIA) that can operate at a higher bandwidth and lower noise compared to conventional TIAs. The TIA employs a data path with both feedback impedance and feedback capacitance for improved performance. The feedback impedance includes at least two resistors in series and at least one shunt capacitor, coupled between the at least two resistors, that helps to extend the circuit bandwidth and improve SNR at the same time. The capacitance value of the shunt capacitor can be selected based on both the bandwidth and noise. In one example, the TIA includes: (1) a biasing path, and (2) a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. An optical receiver and a circuit having the TIA are also disclosed.

    SIGNALING OVER RC-DOMINATED TRANSMISSION LINES
    5.
    发明公开
    SIGNALING OVER RC-DOMINATED TRANSMISSION LINES 审中-公开

    公开(公告)号：US20240214028A1

    公开(公告)日：2024-06-27

    申请号：US18086351

    申请日：2022-12-21

    Applicant: NVIDIA Corporation

    Inventor： John Poulton ,  Sanquan Song ,  Xi Chen ,  Walker Turner ,  Yoshinori Nishi ,  John M. Wilson

    IPC: H04B3/04

    CPC classification number: H04B3/04

    Abstract: The disclosure provides a signaling link that overcomes or at least reduces the limitations of RC-dominated signaling wires, improving both the bandwidth and the power consumption of signaling circuits. Both an AC and a DC signaling link are disclosed. In one example, a signaling link is provided that includes: (1) a transmitter including a passive equalizer, (2) an over-terminated receiver, and (3) a lossy channel having a first end connected to the passive equalizer and a second end connected to the receiver, wherein the lossy channel has a channel characteristic impedance that is lower than a terminating impedance of the passive equalizer and a termination impedance of the receiver.

    Frequency-locked and phase-locked loop-based clock glitch detection for security
    6.
    发明授权
    Frequency-locked and phase-locked loop-based clock glitch detection for security 有权

    公开(公告)号：US11962312B2

    公开(公告)日：2024-04-16

    申请号：US18106398

    申请日：2023-02-06

    Applicant: NVIDIA Corporation

    Inventor： Sanquan Song ,  Stephen G. Tell ,  Nikola Nedovic

    IPC: H03L7/099 ,  H03L7/089

    CPC classification number: H03L7/099 ,  H03L7/0891

    Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

    TRANSIMPEDANCE AMPLIFIER FOR CONVERTING ELECTRICAL CURRENTS TO VOLTAGES
    7.
    发明申请
    TRANSIMPEDANCE AMPLIFIER FOR CONVERTING ELECTRICAL CURRENTS TO VOLTAGES 有权

    公开(公告)号：US20210242837A1

    公开(公告)日：2021-08-05

    申请号：US16778895

    申请日：2020-01-31

    Applicant: Nvidia Corporation

    Inventor： Sanquan Song ,  John Poulton ,  Carl Thomas Gray

    IPC: H03F1/08 ,  H03F1/26

    Abstract: The disclosure provides an improved transimpedance amplifier (TIA) that can operate at a higher bandwidth and lower noise compared to conventional TIAs. The TIA employs a data path with both feedback impedance and feedback capacitance for improved performance. The feedback impedance includes at least two resistors in series and at least one shunt capacitor, coupled between the at least two resistors, that helps to extend the circuit bandwidth and improve SNR at the same time. The capacitance value of the shunt capacitor can be selected based on both the bandwidth and noise. In one example, the TIA includes: (1) a biasing path, and (2) a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. An optical receiver and a circuit having the TIA are also disclosed.

    FREQUENCY-LOCKED AND PHASE-LOCKED LOOP-BASED CLOCK GLITCH DETECTION FOR SECURITY
    8.
    发明公开
    FREQUENCY-LOCKED AND PHASE-LOCKED LOOP-BASED CLOCK GLITCH DETECTION FOR SECURITY 审中-公开

    公开(公告)号：US20230387922A1

    公开(公告)日：2023-11-30

    申请号：US18106398

    申请日：2023-02-06

    Applicant: NVIDIA Corporation

    Inventor： Sanquan Song ,  Stephen G. Tell ,  Nikola Nedovic

    IPC: H03L7/099 ,  H03L7/089

    CPC classification number: H03L7/099 ,  H03L7/0891

    Abstract: A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes digital logic that in turn includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value. The digital logic further includes a loop filter coupled between the glitch detector and the oscillator. The loop filter variably adjusts the oscillator based on a frequency of each of the multiple samples to control an output frequency of each of the multiple different phases of the oscillator.

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