公开(公告)号：US20090083480A1

公开(公告)日：2009-03-26

申请号：US12292269

申请日：2008-11-14

申请人： Naoki Moritoki ,  Nobuyuki Minowa

发明人： Naoki Moritoki ,  Nobuyuki Minowa

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/067 ,  G06F3/0689

摘要： The present invention comprises a memory, a plurality of access portions for accessing the memory, a memory adapter for controlling access to the memory from the plurality of access portions, and a response-type path (R path) and a throughput-type path (T path) which communicatively connect the respective access portions, and the memory adapter. The amount of information capable of being transferred by the R path within the same period of time is smaller than that of the T path, but the length of time from the sending of information until the receipt of a response thereto is shorter for the R path than for the T path. The length of time from the sending of information until the receipt of a response thereto is longer for the T path than for the R path, but the amount of information capable of being transferred by the T path within the same period of time is greater than that of the R path. The memory adapter preferentially allows access to the memory via the R path than access to memory via the T path.

摘要翻译： 本发明包括存储器，用于访问存储器的多个访问部分，用于控制从多个访问部分访问存储器的存储器适配器，以及响应型路径（R路径）和吞吐量类型路径 T路径），其通信地连接各个访问部分，以及存储器适配器。 在同一时间段内由R路径传输的信息量小于T路径的信息量，但从发送信息直到接收到响应的时间长度为R路径较短 比T路径。 从发送信息到收到响应的时间长度比T路径长，而不是在同一时间段内由T路径传输的信息量大于 那R路径。 存储器适配器优先通过R路径访问存储器，而不是通过T路径访问存储器。

公开(公告)号：US07395392B2

公开(公告)日：2008-07-01

申请号：US11144628

申请日：2005-06-06

申请人： Nobuyuki Minowa

发明人： Nobuyuki Minowa

IPC分类号： G06F12/14

CPC分类号： G06F3/0656 ,  G06F3/061 ,  G06F3/067

摘要： A controller and one or more intermediate devices that are connected to a plurality of processors and this controller so that communications are possible are provided. A first access message including a designated value designated by the processor is transmitted to the controller by a first intermediate device connected to the processor. The controller specifies a local memory address corresponding to the designated value included in the first access message, and transmits a second access message including this specified local memory address to two or more other processors. The two or more other processors or second intermediate devices that are connected to these processors access local memory regions of two or more local memories respectively corresponding to two or more other processors, which are local memory regions corresponding to the local memory addresses included in the second access message.

摘要翻译： 提供了连接到多个处理器的控制器和一个或多个中间设备，并且该控制器提供了可能的通信。 包括由处理器指定的指定值的第一访问消息通过连接到处理器的第一中间设备传送到控制器。 控制器指定与包括在第一访问消息中的指定值相对应的本地存储器地址，并且将包括该指定的本地存储器地址的第二访问消息发送到两个或更多个其他处理器。 连接到这些处理器的两个或多个其他处理器或第二中间设备访问分别对应于两个或更多个其他处理器的两个或更多个本地存储器的本地存储器区域，这两个或多个其他处理器是对应于包括在第二个中的本地存储器地址的本地存储器区域 访问消息。

公开(公告)号：US20060236052A1

公开(公告)日：2006-10-19

申请号：US11144628

申请日：2005-06-06

申请人： Nobuyuki Minowa

发明人： Nobuyuki Minowa

IPC分类号： G06F12/14

CPC分类号： G06F3/0656 ,  G06F3/061 ,  G06F3/067

摘要： A controller and one or more intermediate devices that are connected to a plurality of processors and this controller so that communications are possible are provided. A first access message including a designated value designated by the processor is transmitted to the controller by a first intermediate device connected to the processor. The controller specifies a local memory address corresponding to the designated value included in the first access message, and transmits a second access message including this specified local memory address to two or more other processors. The two or more other processors or second intermediate devices that are connected to these processors access local memory regions of two or more local memories respectively corresponding to two or more other processors, which are local memory regions corresponding to the local memory addresses included in the second access message.

摘要翻译： 提供了连接到多个处理器的控制器和一个或多个中间设备，并且该控制器提供了可能的通信。 包括由处理器指定的指定值的第一访问消息通过连接到处理器的第一中间设备传送到控制器。 控制器指定与包括在第一访问消息中的指定值相对应的本地存储器地址，并且将包括该指定的本地存储器地址的第二访问消息发送到两个或更多个其他处理器。 连接到这些处理器的两个或多个其他处理器或第二中间设备访问分别对应于两个或更多个其他处理器的两个或更多个本地存储器的本地存储器区域，这两个或多个其他处理器是对应于包括在第二个 访问消息。

公开(公告)号：US20050257004A1

公开(公告)日：2005-11-17

申请号：US11188004

申请日：2005-07-25

申请人： Kazuhisa Fujimoto ,  Akira Fujibayashi ,  Nobuyuki Minowa

发明人： Kazuhisa Fujimoto ,  Akira Fujibayashi ,  Nobuyuki Minowa

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0626 ,  G06F3/0635 ,  G06F3/0689 ,  G06F11/1666 ,  G06F11/2007 ,  G06F11/201 ,  G06F12/084 ,  G06F12/0866

摘要： This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed. Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed. A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.

摘要翻译： 本发明涉及一种磁盘阵列控制器。 需要大量的存储器件系统可操作而不中断。 此外，为了应对最近开放系统的趋势，需要这种系统的性能和容量的可扩展性。 通常，将一个将通道接口部分连接到共享存储器部分的内部总线和共享存储器部分的盘接口部分安装在一个盘片上，并且其上安装了通道接口和其他包装。 如果内部总线出现故障，整个系统的运行必须停止。 另外还有一个问题是内部总线的性能是固定的。 根据本发明的磁盘阵列控制器包括其上安装有通道接口部分和磁盘接口部分的接口拼盘，其上安装有共享存储器部分的存储器盘片和将接口盘连接到存储器盘片的电缆 以解决上述问题。

公开(公告)号：US06801983B2

公开(公告)日：2004-10-05

申请号：US09141601

申请日：1998-08-28

申请人： Tetsuya Abe ,  Nobuyuki Minowa

发明人： Tetsuya Abe ,  Nobuyuki Minowa

IPC分类号： G06F1200

CPC分类号： G06F11/2007

摘要： An apparatus for use in a storage device having at least two clusters, each including a disk control device having a plurality of channel controllers that send and receive commands and data to and from an upper system, a plurality of disk controllers that control disk units, and a cache that temporarily stores data between the upper system and the disk units. The apparatus includes a first bus included in a first cluster. The first bus is connected to the channel controller, the disk controller and the cache of the first cluster. A second bus is included in a second cluster. The second bus is connected to the channel controller, the disk controller and the cache of the second cluster. A common resource is connected to the first bus of the first cluster and the second bus of the second cluster. The common resource includes a specified set of data which is commonly accessible from each of the channel controllers or the disk controllers of the clusters.

摘要翻译： 一种用于具有至少两个群集的存储设备的设备，每个群集包括具有多个信道控制器的盘控制设备，所述多个信道控制器向上系统发送命令和数据，以及控制盘单元的多个盘控制器， 以及在上层系统和磁盘单元之间临时存储数据的高速缓存。 该装置包括包括在第一集群中的第一总线。 第一个总线连接到通道控制器，磁盘控制器和第一个集群的缓存。 第二个总线包含在第二个集群中。 第二个总线连接到通道控制器，磁盘控制器和第二个集群的缓存。 公共资源连接到第一集群的第一总线和第二集群的第二总线。 公共资源包括通常可以从集群的每个信道控制器或磁盘控制器访问的指定的一组数据。

公开(公告)号：US06502167B1

公开(公告)日：2002-12-31

申请号：US09526461

申请日：2000-03-16

申请人： Atsushi Tanaka ,  Akira Fujibayashi ,  Kazuhisa Fujimoto ,  Hiroki Kanai ,  Nobuyuki Minowa ,  Hikari Mikami ,  Makoto Asari

发明人： Atsushi Tanaka ,  Akira Fujibayashi ,  Kazuhisa Fujimoto ,  Hiroki Kanai ,  Nobuyuki Minowa ,  Hikari Mikami ,  Makoto Asari

IPC分类号： G06F1200

CPC分类号： G06F11/201 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/2007 ,  G06F11/2089 ,  G06F11/2097

摘要： The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one ratio between each interface and respective access paths, a selector connected to the plurality of interfaces, and a cache memory connected to the selector. The number of access paths between the selector and the plurality of interfaces is greater than the number of access paths between the cache memory and the selector. Each processor performs dual writing in the duplicated shared memories.

摘要翻译： 磁盘阵列控制器包括与各个处理器的多个接口，用于与主计算机或磁盘设备连接，在每个接口和相应的访问路径之间以一比一的比例连接的复制共享存储器，连接到多个接口的选择器，以及 连接到选择器的高速缓冲存储器。 选择器和多个接口之间的访问路径的数量大于高速缓冲存储器和选择器之间的访问路径的数量。 每个处理器在重复的共享存储器中执行双重写入。

公开(公告)号：US06385681B1

公开(公告)日：2002-05-07

申请号：US09358374

申请日：1999-07-21

申请人： Kazuhisa Fujimoto ,  Atsushi Tanaka ,  Akira Fujibayashi ,  Hiroki Kanai ,  Nobuyuki Minowa

发明人： Kazuhisa Fujimoto ,  Atsushi Tanaka ,  Akira Fujibayashi ,  Hiroki Kanai ,  Nobuyuki Minowa

IPC分类号： G06F1340

CPC分类号： G06F3/0611 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0658 ,  G06F3/0683 ,  G06F3/0689 ,  G06F12/084 ,  G06F12/0866 ,  G06F13/122

摘要： A disk array control device which includes a plurality of channel interface (IF) units, a plurality of disk IF units, a cache memory unit, and a shared memory unit. The connection system between the plurality of channel IF units and plurality of disk IF units and the cache memory unit is different from the connection system between the plurality of channel IF units and plurality of disk IF units and the shared memory unit. In the invention the plurality of channel IF units and the plurality of disk IF units are connected via a selector to the cache memory unit, whereas the plurality of channel IF units and the plurality of disk IF units are directly connected to the shared memory unit with no selectors.

摘要翻译： 一种磁盘阵列控制装置，包括多个通道接口（IF）单元，多个磁盘中频单元，高速缓冲存储器单元和共享存储单元。 多个信道IF单元与多个盘IF单元和高速缓冲存储器单元之间的连接系统与多个信道IF单元与多个盘IF单元和共享存储单元之间的连接系统不同。 在本发明中，多个信道IF单元和多个盘IF单元经由选择器连接到高速缓冲存储器单元，而多个信道IF单元和多个盘IF单元直接连接到共享存储器单元，具有 没有选择器

公开(公告)号：US08219760B2

公开(公告)日：2012-07-10

申请号：US12526663

申请日：2009-04-06

申请人： Hideaki Fukuda ,  Nobuyuki Minowa ,  Naoki Moritoki ,  Masanori Takada ,  Masato Shimizu

发明人： Hideaki Fukuda ,  Nobuyuki Minowa ,  Naoki Moritoki ,  Masanori Takada ,  Masato Shimizu

IPC分类号： G06F13/00 ,  G06F12/14

CPC分类号： G06F3/0659 ,  G06F3/0614 ,  G06F3/0637 ,  G06F3/0658 ,  G06F3/0683 ,  G06F12/0284 ,  G06F12/1458 ,  G06F12/1483

摘要： Provided is a storage subsystem capable of maintaining the reliability of I/O processing to a host apparatus, even if there is an unauthorized access from a processor core to a switch circuit, by applying a multi-core system to a processor. A multi-core processor is applied to a second logical address space that is different from a first logical address space to be commonly applied to multiple controlled units such as a host interface to be accessed by the processor. The switch circuit determines the processor core that issued an access based on an address belonging to a second address space, and maps an address containing in an access from the processor core to an address of a first address space.

摘要翻译： 提供了一种存储子系统，即使从处理器核心到开关电路的未经授权的访问，通过将多核系统应用于处理器，也能够维持对主机设备的I / O处理的可靠性。 多核处理器被应用于不同于第一逻辑地址空间的第二逻辑地址空间，以将其通常应用于多个受控单元，例如由处理器访问的主机接口。 开关电路基于属于第二地址空间的地址确定发出访问的处理器核心，并将包含在从处理器核心的访问中的地址映射到第一地址空间的地址。

公开(公告)号：US07454656B2

公开(公告)日：2008-11-18

申请号：US10937311

申请日：2004-09-10

申请人： Naoki Okada ,  Kenji Mori ,  Nobuyuki Minowa

发明人： Naoki Okada ,  Kenji Mori ,  Nobuyuki Minowa

IPC分类号： G06F11/00

CPC分类号： G06F11/1441

摘要： According to the present invention, in cases where a CHA function and a DKA function are mounted within a single package, a battery power supply that is used during the occurrence of power supply trouble is effectively utilized so that the supply of power can be separately controlled for each function. A CHA part and DKA part are disposed in a single control package. When trouble such as a power outage is detected, the CHA part blocks access requests from the host, and initiates end processing. When the end processing of the CHA part is completed, the package internal power supply control part stops the clock supply to the CHA part. Then, when the DKA part completes destage processing, the package internal power supply control part stops the supply of power to the DKA part. The power consumption of the package is lowered in stages in accordance with the progress of the end processing.

摘要翻译： 根据本发明，在单个封装中安装有CHA功能和DKA功能的情况下，有效地利用在发生电源故障期间使用的电池电源，从而可以单独控制电力供应 对于每个功能 CHA部件和DKA部件设置在单个控制包装中。 当检测到停电等故障时，CHA部分阻止来自主机的访问请求，并开始结束处理。 当CHA部件的结束处理完成时，封装内部电源控制部分停止对CHA部件的时钟供给。 然后，当DKA部件完成停止处理时，封装内部电源控制部分停止向DKA部件供电。 根据最终处理的进度，包装的功耗逐级降低。

公开(公告)号：US20080046672A1

公开(公告)日：2008-02-21

申请号：US11873995

申请日：2007-10-17

申请人： Masanori FUJII ,  Yasuo Inoue ,  Nobuyuki Minowa

发明人： Masanori FUJII ,  Yasuo Inoue ,  Nobuyuki Minowa

IPC分类号： G06F12/00

CPC分类号： G06F11/1417

摘要： A PLD is interposed on the communication route between a microprocessor (hereinbelow called MP) and boot memories. The boot memories store MP start-up data needed to start up the MP and start-up protection code constituting protection code for the MP start-up data. The PLD reads the MP start-up data and the start-up protection code thereof from the boot memories, performs, in hardware fashion, a check of the validity of the MP start-up data using this start-up protection code and, if a negative check result is obtained, resets the MP and if a positive check result is obtained, inputs the start-up data that is thus read to the MP.

摘要翻译： PLD插入在微处理器（以下称为MP）和引导存储器之间的通信路由上。 启动存储器存储启动MP所需的MP启动数据和构成MP启动数据的保护代码的启动保护代码。 PLD从引导存储器读取MP启动数据及其启动保护代码，以硬件方式执行使用该启动保护代码检查MP启动数据的有效性，并且如果 获得负检查结果，复位MP，如果获得正检查结果，则将由此读取的启动数据输入到MP。