Abstract:
A method for displaying error rates of data channels of a display is provided. A timing controller of the display repeatedly transmits a test signal with a specific format to a first and a second source drivers of the display via a first and a second data channels of the display. During testing, a first number and a second number of times of the first source driver and the second source driver determining that the received test signal does not have the specific format are counted respectively. The first and the second source drivers control displaying of a first area and a second area of a panel of the display respectively according to the counted first and second numbers of times. Accordingly, the error rates of the data channels are presented on the panel of the display in a way that the error rates could be recognized more easily.
Abstract:
A source driver includes a first drive channel circuit, a voltage controller and a first programmable voltage buffer unit. The first drive channel circuit receives a first pixel data from the timing controller via a data bus, converts the first pixel data to a first drive voltage according to a first reference voltage group, and drives a display panel by the first drive voltage. The voltage controller receives a voltage command from the timing controller, generates and changes a first reference voltage configuration data according to the voltage command. The first programmable voltage buffer unit is coupled to the voltage controller and the first drive channel circuit, and receives the first reference voltage configuration data to generate and adjust the first reference voltage group for applying to the first drive channel circuit. Furthermore, a method for updating a new gamma curve by the source driver is also provided.
Abstract:
A display driver, which comprises: a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising at least one first predetermined voltage level; a first image data providing apparatus, for outputting a first image data; and a detection controlling circuit, for determining if an output terminal of the first image data providing apparatus is pre-charged to the first predetermined voltage level according to a relation between an absolute value of a voltage level of the first image data and an absolute value of the first predetermined voltage level.
Abstract:
A clock-embedded data generating apparatus and transmission method are disclosed. The steps of the transmission method include: generating a plurality of preamble signals according to a number sequence, where each of the preamble signals has a plurality of bits. The number sequence includes a plurality of values, and the bits of each of the preamble signals are decided by each of the corresponding values; transmitting the preamble signals during a plurality of preamble signal transmitting periods respectively, and transmitting a plurality of data signal during a plurality of data signal transmitting periods respectively.
Abstract:
A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, includes adjusting a selecting signal according to a clock signal; selecting one of a plurality of scrambling generating units according to the selecting signal to generate a timing scrambling signal; and generating scrambling data for the plurality of source driving devices according to the timing scrambling signal.
Abstract:
A data transmission device includes a data division unit for receiving an original transmission data and dividing the original transmission data into a plurality of division data; a data generation unit for generating a plurality of packet data according to the plurality of division data and a plurality of clock data, wherein each of the clock data is a multi-bit data; and a data output unit for outputting the plurality of packet data to a data reception device; where each of the packet data includes a division data and a clock data, each of the packet data corresponds to a packet data period, and the division data corresponds to a division data period of the packet data period and the clock data corresponds to a clock period of the packet data period.
Abstract:
A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.
Abstract:
A liquid crystal display apparatus, a source driver, and a method for controlling polarity of driving signals thereof are provided. The source driver includes a signal receiving interface, a decoder, and a controller. The signal receiving interface receives an image data stream or an indication signal. The decoder obtains controlling information from the image data stream or the indication signal. The controller receives the controlling information and decides a plurality of source driving signals generated by the source driver according to the controlling information.
Abstract:
A liquid crystal display apparatus, a source driver, and a method for controlling polarity of driving signals thereof are provided. The source driver includes a signal receiving interface, a decoder, and a controller. The signal receiving interface receives an image data stream or a data input/output indication signal. The decoder obtains polarity controlling information from the image data stream or the data input/output indication signal. The controller receives the polarity controlling information and decides driving polarities of a plurality of source driving signals generated by the source driver according to the polarity controlling information.
Abstract:
The present invention discloses an integrated source driver for a liquid crystal display device. The integrated source driver includes a reference voltage generating circuit, for providing a plurality of adjustable voltage ranges within a supply voltage and a ground level, and a reference voltage selecting circuit, including a plurality of digital to analog converters, for selecting and generating a plurality of internal reference voltages from the plurality of adjustable voltage ranges, respectively. The plurality of adjustable voltage ranges decrease progressively.