Inground pool wall and deck support
    21.
    发明授权
    Inground pool wall and deck support 有权
    地下池壁和甲板支撑

    公开(公告)号:US09447594B2

    公开(公告)日:2016-09-20

    申请号:US13487839

    申请日:2012-06-04

    IPC分类号: E04H4/00 E04H4/14

    摘要: The present invention provides a pool wall and deck support member including modular and symmetrical upper and lower halves adapted to be interconnected to one another to form a unitary support member. Each half is essentially V-shaped with the bottom of the V having a pair of fastening elements disposed thereon and adapted to securely engage corresponding fastening elements disposed on the bottom of the V of the opposite half. Disposed on the ends of the upwardly extending legs of the V-shaped members are fastening elements that are adapted to engage a cross bar that extends across the V-shaped member.

    摘要翻译: 本发明提供一种池壁和甲板支撑构件,其包括适于彼此互连以形成整体支撑构件的模块化和对称的上半部和下半部。 每个半部基本上是V形的,其中V的底部具有一对紧固元件,其上设置有一对紧固元件,并且适于牢固地接合设置在相对的一半的V的底部上的对应的紧固元件。 在V形构件的向上延伸的腿的端部上设置有紧固元件,其适于接合跨过V形构件延伸的横杆。

    Apparatus and method for reducing defects in a semiconductor lithographic process
    25.
    发明授权
    Apparatus and method for reducing defects in a semiconductor lithographic process 有权
    用于减少半导体光刻工艺中的缺陷的装置和方法

    公开(公告)号:US06222936B1

    公开(公告)日:2001-04-24

    申请号:US09394871

    申请日:1999-09-13

    IPC分类号: G06K900

    CPC分类号: G03F7/70616 G03F7/7065

    摘要: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.

    摘要翻译: 用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案,以模拟半导体产品的实际处理条件。 然后使用晶片检查系统检查抗蚀剂图案。 在线低电压扫描电子显微镜(SEM)系统评估和分类缺陷类型,实现替代处理规范的生成。 然后可以通过在不同晶片上形成图案来测试替代处理规范,然后进行分裂式测试以分析不同晶片上的图案,以与现有的光刻工艺和生产资格进行比较。

    Method for reducing defects in a semiconductor lithographic process
    26.
    发明授权
    Method for reducing defects in a semiconductor lithographic process 失效
    用于减少半导体光刻工艺中的缺陷的方法

    公开(公告)号:US5985497A

    公开(公告)日:1999-11-16

    申请号:US17678

    申请日:1998-02-03

    IPC分类号: G03F7/20 G03F9/00

    CPC分类号: G03F7/70616 G03F7/7065

    摘要: An arrangement for optimizing a lithographic process forms a pattern on a silicon wafer using a photocluster cell system to simulate an actual processing condition for a semiconductor product. The resist pattern is then inspected using a wafer inspection system. An in-line low voltage scanning electron microscope (SEM) system reviews and classifies defect types, enabling generation of an alternative processing specification. The alternative processing specification can then be tested by forming patterns on different wafers, and then performing split-series testing to analyze the patterns on the different wafers for comparison with the existing lithographic process and qualification for production.

    摘要翻译: 用于优化光刻工艺的布置使用光集电池系统在硅晶片上形成图案,以模拟半导体产品的实际处理条件。 然后使用晶片检查系统检查抗蚀剂图案。 在线低电压扫描电子显微镜(SEM)系统评估和分类缺陷类型,实现替代处理规范的生成。 然后可以通过在不同晶片上形成图案来测试替代处理规范,然后进行分裂式测试以分析不同晶片上的图案,以与现有的光刻工艺和生产资格进行比较。