公开(公告)号：US20120057650A1

公开(公告)日：2012-03-08

申请号：US13222471

申请日：2011-08-31

申请人： Stephen Felix ,  Steve Allpress

发明人： Stephen Felix ,  Steve Allpress

IPC分类号： H04L25/03

CPC分类号： H04L27/367 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2201/3206 ,  H04B1/707 ,  H04L27/2614

摘要： A method for limiting peak-to-average power of a signal transmitted from a power amplifier. The method comprises: applying a pulse-shape filter to a first signal, thereby generating a second signal being a filtered version of the first signal; and outputting the second signal for transmission from a power amplifier. The method further comprises: applying each of a plurality of predictor filters to a respective instance of the first signal, each predictor filter approximating the application of the pulse-shape filter to the first signal based on a different respective set of filter coefficients, and each thereby generating a respective third signal. The method also further comprises determining an indicator of amplitude of each of the third signals, selecting the indicator corresponding to the largest of those amplitudes, generating a modifier based on the selected indicator, and using the modifier to limit the first signal prior to applying the pulse-shape filter.

摘要翻译： 一种用于限制从功率放大器发送的信号的峰值与平均功率的方法。 该方法包括：对第一信号施加脉冲形滤波器，从而产生作为第一信号的滤波版本的第二信号; 并从功率放大器输出用于传输的第二信号。 该方法还包括：将多个预测滤波器中的每一个应用于第一信号的相应实例，每个预测器滤波器基于不同的相应滤波器系数集合近似将脉冲形滤波器应用于第一信号，并且每个 从而产生相应的第三信号。 该方法还包括确定每个第三信号的幅度指标，选择对应于最大幅度的指示符，基于所选择的指示符生成修改符，并且使用修饰符来限制第一信号， 脉冲形滤波器。

公开(公告)号：US20090147888A1

公开(公告)日：2009-06-11

申请号：US12330905

申请日：2008-12-09

申请人： Stephen Felix ,  Colman Hegarty

发明人： Stephen Felix ,  Colman Hegarty

IPC分类号： H04L7/00 ,  H04L7/04 ,  H04L27/06

CPC分类号： H04L7/0008

摘要： The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

摘要翻译： 本发明提供一种接收机，包括数据输入和选通输入。 当数据信号中的两个连续位相同时，选通信号转换。 接收机包括用于从数据和选通信号的组合产生恢复的时钟信号的组合装置。 接收机还包括第一采样级，其被布置为根据恢复的时钟信号对数据信号进行采样，第一采样级包括多个采样电路，并且被布置为使用交替的采样电路来获得数据信号的连续采样 。 第二采样级被设置为根据本地系统时钟信号对来自第一采样级的数据进行采样。

公开(公告)号：US5684424A

公开(公告)日：1997-11-04

申请号：US468726

申请日：1995-06-06

申请人： Stephen Felix ,  Russell Edwin Francis

发明人： Stephen Felix ,  Russell Edwin Francis

IPC分类号： H03K5/13 ,  G06F1/10 ,  H03K5/00 ,  H03K5/15 ,  H03K19/003 ,  H03K3/00

CPC分类号： H03K5/15046 ,  G06F1/10 ,  H03K19/00323

摘要： A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.

摘要翻译： 用于在电路内的不同位置产生脉冲的脉冲发生器具有用于在接收到第一输入脉冲之后进行时间依赖性操作的第一电路501和用于在接收到第二输入脉冲之后执行时间相关操作的第二电路502 第一次输入脉冲后。 第三电路503响应于第一和第二电路501,502中的每一个达到相应的预定条件，使得由第三电路503产生输出脉冲，时间取决于第一和第二电路501和502的平均工作持续时间 。

公开(公告)号：US09639327B2

公开(公告)日：2017-05-02

申请号：US13638763

申请日：2011-04-07

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： G06F7/523 ,  G06F7/53

CPC分类号： G06F7/523 ,  G06F7/53

摘要： A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

公开(公告)号：US07933405B2

公开(公告)日：2011-04-26

申请号：US11102266

申请日：2005-04-08

申请人： Simon Knowles ,  Stephen Felix

发明人： Simon Knowles ,  Stephen Felix

IPC分类号： H04L9/00

CPC分类号： G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

摘要： According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

摘要翻译： 根据本发明的实施例，公开了一种数据处理单元，其操作方法，计算机程序产品和指令。 在根据本发明的一个实施例中，提供了一种用于计算机处理器的数据处理单元，该数据处理单元包括一个深度寄存器访问机制，能够对从计算机的寄存器文件访问的至少一个数据操作数执行置换操作 处理器，与（i）数据操作数的寄存器访问和（ii）对操作数的数据处理操作的执行串联执行的置换操作。

公开(公告)号：US20100225351A1

公开(公告)日：2010-09-09

申请号：US12713412

申请日：2010-02-26

申请人： Stephen Felix

发明人： Stephen Felix

IPC分类号： H03K19/0175 ,  H01L21/02

CPC分类号： H03K3/356139 ,  Y10T29/41 ,  Y10T29/49117

摘要： A logic circuit latch including an input stage for receiving a logical input signal and a pair of differential amplifiers, each having an input operatively coupled to the input stage, and at least one of them having an output arranged to supply the logical output of the latch. Each of the differential amplifiers includes a transistor connected as a load, and an output of each of the differential amplifiers is coupled to bias the load transistor of the other differential amplifier. If the latch switches from the transparent state to the closed state while the logical input signal is transitioning between logical levels, the differential amplifiers drive up the logical output of the latch if the logical input signal transitions from a first to a second logical level, and drive down the logical output of the latch if the input signal transitions from the second to the first logical level.

摘要翻译： 逻辑电路锁存器，包括用于接收逻辑输入信号的输入级和一对差动放大器，每个差分放大器具有可操作地耦合到输入级的输入，并且它们中的至少一个具有布置成提供锁存器的逻辑输出的输出 。 每个差分放大器包括作为负载连接的晶体管，并且每个差分放大器的输出被耦合以偏置另一个差分放大器的负载晶体管。 如果逻辑输入信号在逻辑电平之间转换时，锁存器从透明状态切换到关闭状态，则如果逻辑输入信号从第一逻辑电平转换到第二逻辑电平，则差分放大器驱动锁存器的逻辑输出，并且 如果输入信号从第二逻辑电平转换到第一逻辑电平，则驱动锁存器的逻辑输出。

公开(公告)号：US07539141B2

公开(公告)日：2009-05-26

申请号：US10855483

申请日：2004-05-28

申请人： Matthew Mattina ,  George Z. Chrysos ,  Stephen Felix

发明人： Matthew Mattina ,  George Z. Chrysos ,  Stephen Felix

IPC分类号： H04L12/26 ,  H04L12/28

CPC分类号： H04L12/43 ,  H04L12/427 ,  H04L47/10

摘要： Embodiments of the present invention are related in general to data flow control in a network and in particular to synchronous packet flow control in a ring interconnect. An embodiment of a method may include rejecting an arriving packet at a destination node on a semiconductor chip's ring interconnect, e.g., an unbuffered, synchronous ring interconnect, if all of the destination node's buffers are not available, leaving the rejected packet on the ring interconnect to continue traversing the ring, and accepting the rejected packet upon arrival at the destination node, if a buffer is available. In an alternate embodiment, a method may include tracking the rejected packet as the rejected packet traverses the ring interconnect. An embodiment of an apparatus may include a semiconductor chip having a bidirectional ring interconnect and multiple nodes coupled to the bidirectional ring interconnect. Each node may have a buffer to store packets that arrive on the ring interconnect, if the buffer is available, and to reject packets that arrive, if the buffer is not available. These embodiments provide efficient flow control of packets on unbuffered, synchronous ring interconnects. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例一般涉及网络中的数据流控制，特别涉及环形互连中的同步分组流控制。 方法的实施例可以包括在半导体芯片的环形互连（例如，无缓冲的同步环形互连）上的目的地节点处拒绝到达的分组，如果所有目的地节点的缓冲器都不可用，则将拒绝的分组留在环形互连 继续遍历环，并且如果缓冲器可用，则在到达目的地节点时接受被拒绝的分组。 在替代实施例中，一种方法可以包括在拒绝的分组穿过环形互连时跟踪被拒绝的分组。 装置的实施例可以包括具有双向环互连和耦合到双向环互连的多个节点的半导体芯片。 每个节点可以具有缓冲器来存储到达环形互连上的分组，如果缓冲器可用，并且如果缓冲器不可用，则拒绝到达的分组。 这些实施例提供了在无缓冲的同步环互连上的分组的有效流控制。 示例性应用包括芯片多处理。

公开(公告)号：US20060041715A1

公开(公告)日：2006-02-23

申请号：US10855509

申请日：2004-05-28

申请人： George Chrysos ,  Matthew Mattina ,  Stephen Felix

发明人： George Chrysos ,  Matthew Mattina ,  Stephen Felix

IPC分类号： G06F12/00

CPC分类号： G06F15/8015 ,  G06F15/17337

摘要： Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例通常涉及单个芯片上的多个部件的片上集成，特别是通过双向环形互连对多个处理器的片上集成。 半导体芯片的实施例包括多个处理器，处理器之间共享的地址空间以及耦合处理器和地址空间的双向环形互连。 一种方法的实施例包括计算多个环互连上的分组源和目的地之间的距离，确定传输分组的哪个互连，然后在所确定的互连上传送分组。 实施例在多处理器芯片中提供改进的等待时间和带宽。 示例性应用包括芯片多处理。