公开(公告)号：US08924690B2

公开(公告)日：2014-12-30

申请号：US13482713

申请日：2012-05-29

申请人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

发明人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F1/32

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22

摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

摘要翻译： 一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。 在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。 一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。 在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。 在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。 描述和要求保护其他实施例。

公开(公告)号：US20060150048A1

公开(公告)日：2006-07-06

申请号：US11026633

申请日：2004-12-30

申请人： Ugonna Echeruo ,  George Chrysos ,  John Crawford ,  Shubhendu Mukherjee

发明人： Ugonna Echeruo ,  George Chrysos ,  John Crawford ,  Shubhendu Mukherjee

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F12/1027 ,  G06F2212/1032 ,  G06F2212/652 ,  H04L1/0063

摘要： A method and apparatus for protecting a TLB's VPN from soft errors is described. On a TLB lookup, the incoming virtual address is used to CAM the TLB VPN. In parallel with this CAM operation, parity is computed on the incoming virtual address for the possible page sizes supported by the processor. If a matching VPN is found in the TLB, its payload is read out. The encoded page size is used to select which of the set of pre-computed virtual address parity to compare with the stored parity bit in the TLB entry. This has the advantage of removing the computation of parity on the TLB VPN from the critical path of the TLB lookup. Instead it is now in the TLB fill path.

公开(公告)号：US07710904B2

公开(公告)日：2010-05-04

申请号：US11646874

申请日：2006-12-27

申请人： George Chrysos

发明人： George Chrysos

IPC分类号： H04L12/28 ,  H04L12/56

CPC分类号： H04L12/433

摘要： An apparatus including a ring network, a plurality of nodes on the ring network to act as senders, a node on the ring network to act as a receiver, the receiver having receiver logic to place a token on the ring, the token further having an indication of an activation status, and network logic to pass the token along the ring network from each node to the next after the token is placed on the ring network and to activate the token by setting the indication of the activation status to a value indicating that the token is active at a location on the ring determined so that over a defined period of time, the token is activated in proximity to each sender at approximately the same frequency.

摘要翻译： 一种装置，包括环形网络，环形网络上的多个节点作为发送者，环形网络上的节点充当接收机，接收机具有将令牌放置在环上的接收机逻辑，令牌还具有 指示激活状态，以及网络逻辑，以将令牌沿着环形网络从每个节点传递到下一个令牌放置在环形网络上并通过将激活状态的指示设置为指示该激活状态的值来激活该令牌 令牌在所确定的环上的位置处是活动的，使得在定义的时间段内，令牌以大致相同的频率在每个发送者附近被激活。

公开(公告)号：US07689844B2

公开(公告)日：2010-03-30

申请号：US12005473

申请日：2007-12-27

申请人： George Chrysos

发明人： George Chrysos

IPC分类号： G06F1/32 ,  G06F15/76

CPC分类号： G06F1/3203 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3869

摘要： A technique to control power consumption within a microprocessor. More particularly, embodiments of the invention relate to a technique to control power and performance within one or more microprocessors by enforcing a credit-based instruction execution rate algorithm.

摘要翻译： 一种控制微处理器内功耗的技术。 更具体地，本发明的实施例涉及通过实施基于信用的指令执行速率算法来控制一个或多个微处理器内的功率和性能的技术。

公开(公告)号：US20060143406A1

公开(公告)日：2006-06-29

申请号：US11023882

申请日：2004-12-27

申请人： George Chrysos ,  Matthew Mattina

发明人： George Chrysos ,  Matthew Mattina

IPC分类号： G06F13/28

CPC分类号： G06F12/084 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815

摘要： A method for predicting early write back of owned cache blocks in a shared memory computer system. This invention enables the system to predict which written blocks may be more likely to be requested by another CPU and the owning CPU will write those blocks back to memory as soon as possible after updating the data in the block. If another processor is requesting the data, this can reduce the latency to get that data, reducing synchronization overhead, and increasing the throughput of parallel programs.

公开(公告)号：US20060041715A1

公开(公告)日：2006-02-23

申请号：US10855509

申请日：2004-05-28

申请人： George Chrysos ,  Matthew Mattina ,  Stephen Felix

发明人： George Chrysos ,  Matthew Mattina ,  Stephen Felix

IPC分类号： G06F12/00

CPC分类号： G06F15/8015 ,  G06F15/17337

摘要： Embodiments of the present invention are related in general to on-chip integration of multiple components on a single die and in particular to on-chip integration of multiple processors via a bidirectional ring interconnect. An embodiment of a semiconductor chip includes a plurality of processors, an address space shared between the processors, and a bidirectional ring interconnect to couple the processors and the address space. An embodiment of a method includes calculating distances between a packet source and destination on multiple ring interconnects, determining on which interconnect to transport the packet, and then transporting the packet on the determined interconnect. Embodiments provide improved latency and bandwidth in a multiprocessor chip. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例通常涉及单个芯片上的多个部件的片上集成，特别是通过双向环形互连对多个处理器的片上集成。 半导体芯片的实施例包括多个处理器，处理器之间共享的地址空间以及耦合处理器和地址空间的双向环形互连。 一种方法的实施例包括计算多个环互连上的分组源和目的地之间的距离，确定传输分组的哪个互连，然后在所确定的互连上传送分组。 实施例在多处理器芯片中提供改进的等待时间和带宽。 示例性应用包括芯片多处理。

公开(公告)号：US08190863B2

公开(公告)日：2012-05-29

申请号：US10884359

申请日：2004-07-02

申请人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

发明人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F13/00 ,  G06F13/28 ,  G06F1/00

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22

摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

摘要翻译： 一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。 在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。 一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。 在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。 在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。 描述和要求保护其他实施例。

公开(公告)号：US20070168712A1

公开(公告)日：2007-07-19

申请号：US11282213

申请日：2005-11-18

申请人： Paul Racunas ,  Matthew Mattina ,  George Chrysos ,  Shubhendu Mukherjee

发明人： Paul Racunas ,  Matthew Mattina ,  George Chrysos ,  Shubhendu Mukherjee

IPC分类号： G06F11/00

CPC分类号： G06F11/1683 ,  G06F11/1637

摘要： Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.

摘要翻译： 描述并要求保护在每个设备上生成请求，比较请求以及将匹配请求转发到服务节点的锁步骤中的两个或多个设备的操作方法。 还描述并要求保护使用该方法的冗余执行系统。

公开(公告)号：US20060026371A1

公开(公告)日：2006-02-02

申请号：US10903675

申请日：2004-07-30

申请人： George Chrysos ,  Ugonna Echeruo ,  Chyi-Chang Miao ,  James Vash

发明人： George Chrysos ,  Ugonna Echeruo ,  Chyi-Chang Miao ,  James Vash

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3824 ,  G06F9/383

摘要： In one embodiment of the present invention, a method includes generating a first order vector corresponding to a first entry in an operation order queue that corresponds to a first memory operation, and preventing a subsequent memory operation from completing until the first memory operation completes. In such a method, the operation order queue may be a load queue or a store queue, for example. Similarly, an order vector may be generated for an entry of a first operation order queue based on entries in a second operation order queue. Further, such an entry may include a field to identify an entry in the second operation order queue. A merge buffer may be coupled to the first operation order queue and produce a signal when all prior writes become visible.

摘要翻译： 在本发明的一个实施例中，一种方法包括生成对应于与第一存储器操作对应的操作顺序队列中的第一条目的一阶向量，并且防止随后的存储器操作完成直到第一存储器操作完成。 在这种方法中，例如，操作顺序队列可以是加载队列或存储队列。 类似地，可以基于第二操作顺序队列中的条目为第一操作命令队列的条目生成订单向量。 此外，这样的条目可以包括用于标识第二操作命令队列中的条目的字段。 合并缓冲器可以耦合到第一操作顺序队列，并且当所有先前写入变得可见时产生信号。

公开(公告)号：US20050276274A1

公开(公告)日：2005-12-15

申请号：US10855483

申请日：2004-05-28

申请人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

发明人： Matthew Mattina ,  George Chrysos ,  Stephen Felix

IPC分类号： H04L12/427 ,  H04L12/43 ,  H04L12/56 ,  H04L12/28

CPC分类号： H04L12/43 ,  H04L12/427 ,  H04L47/10

摘要： Embodiments of the present invention are related in general to data flow control in a network and in particular to synchronous packet flow control in a ring interconnect. An embodiment of a method may include rejecting an arriving packet at a destination node on a semiconductor chip's ring interconnect, e.g., an unbuffered, synchronous ring interconnect, if all of the destination node's buffers are not available, leaving the rejected packet on the ring interconnect to continue traversing the ring, and accepting the rejected packet upon arrival at the destination node, if a buffer is available. In an alternate embodiment, a method may include tracking the rejected packet as the rejected packet traverses the ring interconnect. An embodiment of an apparatus may include a semiconductor chip having a bidirectional ring interconnect and multiple nodes coupled to the bidirectional ring interconnect. Each node may have a buffer to store packets that arrive on the ring interconnect, if the buffer is available, and to reject packets that arrive, if the buffer is not available. These embodiments provide efficient flow control of packets on unbuffered, synchronous ring interconnects. Exemplary applications include chip multiprocessing.

摘要翻译： 本发明的实施例一般涉及网络中的数据流控制，特别涉及环形互连中的同步分组流控制。 方法的实施例可以包括在半导体芯片的环形互连（例如，无缓冲的同步环形互连）上的目的地节点处拒绝到达的分组，如果所有目的地节点的缓冲器都不可用，则将拒绝的分组留在环形互连 继续遍历环，并且如果缓冲器可用，则在到达目的地节点时接受被拒绝的分组。 在替代实施例中，一种方法可以包括在拒绝的分组穿过环形互连时跟踪被拒绝的分组。 装置的实施例可以包括具有双向环互连和耦合到双向环互连的多个节点的半导体芯片。 每个节点可以具有缓冲器来存储到达环形互连上的分组，如果缓冲器可用，并且如果缓冲器不可用，则拒绝到达的分组。 这些实施例提供了在无缓冲的同步环互连上的分组的有效流控制。 示例性应用包括芯片多处理。