公开(公告)号：US20180165788A1

公开(公告)日：2018-06-14

申请号：US15895652

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Avinash Seetharamaiah ,  Christopher Paul Frascati ,  Jonnala Gadda Nagendra Kumar ,  Colin Christopher Sharp ,  David Rigel Garcia Garcia

IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60 ,  G09G5/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G09G5/00 ,  G09G2330/021

Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.

公开(公告)号：US09928565B2

公开(公告)日：2018-03-27

申请号：US14691358

申请日：2015-04-20

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Avinash Seetharamaiah ,  Christopher Paul Frascati ,  Jonnala gadda Nagendra Kumar ,  Colin Christopher Sharp ,  David Rigel Garcia Garcia

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/00 ,  G06T11/40

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G09G5/00 ,  G09G2330/021

Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.

公开(公告)号：US09799088B2

公开(公告)日：2017-10-24

申请号：US14465371

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Murat Balci ,  Avinash Seetharamaiah ,  Maurice Franklin Ribble ,  Hitendra Mohan Gangani

IPC: G06T1/00 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G09G5/18 ,  G06F9/44

CPC classification number: G06T1/20 ,  G06F9/451 ,  G06T1/60 ,  G06T15/005 ,  G09G5/18

Abstract: In an example, a method for rendering graphics data includes receiving a plurality of commands associated with a plurality of render targets, where the plurality of commands are received in an initial order. The method also includes determining an execution order for the plurality of commands including reordering one or more of the plurality of commands in a different order than the initial order based on data dependencies between commands. The method also includes executing the plurality of commands in the determined execution order.

公开(公告)号：US09530245B2

公开(公告)日：2016-12-27

申请号：US13708118

申请日：2012-12-07

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Joseph Blankenship

IPC: G06T15/80 ,  G06T17/20 ,  G06T11/00 ,  G06T1/60 ,  G06T15/83 ,  G06T17/10 ,  G06T1/20 ,  G06T7/40 ,  G06T15/04 ,  G06F9/445

CPC classification number: G06T15/80 ,  G06F9/445 ,  G06F9/44594 ,  G06T1/20 ,  G06T1/60 ,  G06T7/40 ,  G06T11/00 ,  G06T15/04 ,  G06T15/83 ,  G06T17/10 ,  G06T17/20

Abstract: This disclosure describes techniques for packing multiple shader programs of a common shader program type onto a graphics processing unit (GPU). The techniques may include, for example, causing a plurality of shader programs of a common shader program type to be loaded into an on-chip shader program instruction memory of a graphics processor such that each shader program in the plurality of shader programs resides in the on-chip shader program instruction memory at a common point in time. In addition, various techniques for evicting shader programs from an on-chip shader program instruction memory are described.

Abstract translation: 本公开描述了将共同着色器程序类型的多个着色器程序打包到图形处理单元（GPU）上的技术。 这些技术可以包括例如使得共同着色器程序类型的多个着色器程序被加载到图形处理器的片上着色器程序指令存储器中，使得多个着色器程序中的每个着色器程序驻留在 片上着色器程序指令存储器在公共时间点。 此外，描述了用于从片上着色器程序指令存储器驱逐着色器程序的各种技术。

公开(公告)号：US09483861B2

公开(公告)日：2016-11-01

申请号：US13841584

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Andrew Evan Gruber

IPC: G06T15/00 ,  G06T17/20

CPC classification number: G06T15/005

Abstract: This disclosure describes techniques for using bounding regions to perform tile-based rendering with a graphics processing unit (GPU) that supports an on-chip, tessellation-enabled graphics rendering pipeline. Instead of generating binning data based on rasterized versions of the actual primitives to be rendered, the techniques of this disclosure may generate binning data based on a bounding region that encompasses one or more of the primitives to be rendered. Moreover, the binning data may be generated based on data that is generated by at least one tessellation processing stage of an on-chip, tessellation-enabled graphics rendering pipeline that is implemented by the GPU. The techniques of this disclosure may, in some examples, be used to improve the performance of an on-chip, tessellation-enabled GPU when performing tile-based rendering without sacrificing the quality of the resulting rendered image.

Abstract translation: 本公开描述了使用边界区域来执行基于瓦片的渲染的技术，该图形处理单元（GPU）支持片上，镶嵌的图形渲染流水线。 基于要渲染的实际原语的光栅化版本而不是生成合并数据，本公开的技术可以基于包含要呈现的一个或多个基元的边界区域来生成合并数据。 此外，可以基于由GPU实现的片上，镶嵌使能的图形呈现流水线的至少一个镶嵌处理阶段生成的数据来生成合并数据。 在一些示例中，本公开的技术可以用于在不牺牲所得到的渲染图像的质量的情况下执行基于图块的渲染时，提高片上，镶嵌功能的GPU的性能。

公开(公告)号：US20160180503A1

公开(公告)日：2016-06-23

申请号：US14574807

申请日：2014-12-18

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Murat Balci

IPC: G06T5/00 ,  G06T3/00

CPC classification number: G06T5/002 ,  A61B3/02 ,  A61B3/028 ,  G06T3/0093 ,  G06T2207/10004 ,  G06T2207/20092 ,  G09G5/36 ,  G09G2320/0271 ,  G09G2320/066 ,  G09G2320/08 ,  G09G2354/00

Abstract: An apparatus configured for graphics processing includes a memory configured to store graphics data, and one or more processors in communication with the memory, the one or more processors configured to output, for display, a plurality of test graphics images, receive input indicative of a perception of a user of the computing device of at least one test graphics image from the plurality of test graphics images, determine at least one parameter modification value and generate a corrected graphics image based at least in part on the at least one parameter modification value.

Abstract translation: 配置用于图形处理的装置包括被配置为存储图形数据的存储器和与存储器通信的一个或多个处理器，所述一个或多个处理器被配置为输出多个测试图形图像，用于显示指示一个 对来自多个测试图形图像的至少一个测试图形图像的计算设备的用户的感知确定至少一个参数修改值并且至少部分地基于至少一个参数修改值来生成校正的图形图像。

公开(公告)号：US09230518B2

公开(公告)日：2016-01-05

申请号：US14023170

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Murat Balci ,  Avinash Seetharamaiah ,  Andrew Evan Gruber ,  Alexei Vladimirovich Bourd

IPC: G06T1/00 ,  G06T15/00 ,  G06F15/00 ,  G09G5/399 ,  G06T1/20 ,  G06F9/46 ,  G06T1/60

CPC classification number: G09G5/399 ,  G06F9/46 ,  G06F9/4843 ,  G06F2209/483 ,  G06F2209/509 ,  G06T1/20 ,  G06T1/60

Abstract: This disclosure presents techniques and structures for preemption at arbitrary control points in graphics processing. A method of graphics processing may comprise executing commands in a command buffer, the commands operating on data in a read-modify-write memory resource, double buffering the data in the read-modify-write memory resource, such that a first buffer stores original data of the read-modify-write memory resource and a second buffer stores any modified data produced by executing the commands in the command buffer, receiving a request to preempt execution of the commands in the command buffer before completing all commands in the command buffer, and restarting execution of the commands at the start of the command buffer using the original data in the first buffer.

Abstract translation: 本公开提供在图形处理中的任意控制点处的抢占的技术和结构。 图形处理的方法可以包括在命令缓冲器中执行命令，操作在读 - 修改 - 写存储器资源中的数据的命令，双重缓冲读 - 修改 - 写存储器资源中的数据，使得第一缓冲器存储原始 读取 - 修改 - 写入存储器资源的数据和第二缓冲器存储通过执行命令缓冲器中的命令而产生的任何修改的数据，在完成命令缓冲器中的所有命令之前，接收到抢占执行命令缓冲器中的命令的请求， 并使用第一缓冲器中的原始数据重新启动命令缓冲区开始处的命令。

公开(公告)号：US20150302546A1

公开(公告)日：2015-10-22

申请号：US14691358

申请日：2015-04-20

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Avinash Seetharamaiah ,  Christopher Paul Frascati ,  Jonnala gadda Nagendra Kumar ,  Colin Christopher Sharp ,  David Rigel Garcia Garcia

IPC: G06T1/20 ,  G09G5/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G09G5/00 ,  G09G2330/021

Abstract: A device comprising a graphics processing unit (GPU) includes a memory and at least one processor. The at least one processor may be configured to: receive a GPU command packet that indicates the GPU may select between a direct rendering mode or a binning rendering mode for a portion of a frame to be rendered by the GPU, determine whether to use the direct rendering mode or the binning rendering mode for the portion of the frame to be rendered by the GPU based on at least one of: information in the received command packet or a state of the GPU, and render the portion of the frame using the determined direct rendering mode or the binning rendering mode.

Abstract translation: 包括图形处理单元（GPU）的设备包括存储器和至少一个处理器。 所述至少一个处理器可以被配置为：接收指示GPU可以在用于由GPU呈现的帧的一部分的直接呈现模式或混合渲染模式之间选择的GPU命令分组，确定是否使用直接 基于以下中的至少一个：所接收的命令分组中的信息或GPU的状态中的至少一个，并且使用所确定的直接来渲染所述帧的所述部分，所述渲染模式或所述帧的所述部分将由所述GPU渲染 渲染模式或分箱渲染模式。

公开(公告)号：US09773340B2

公开(公告)日：2017-09-26

申请号：US14738535

申请日：2015-06-12

Applicant: QUALCOMM Incorporated

Inventor： Murat Balci ,  Christopher Paul Frascati ,  Juraj Obert ,  Hitendra Mohan Gangani ,  Avinash Seetharamaiah

IPC: G06T15/06 ,  G06T15/40 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/40

Abstract: A method and apparatus for ray tracing may include a method, manufacture and apparatus for ray tracing that may include dividing a render target into a plurality of bins. Next, a visibility pass is performed using ray tracing to generate a visibility stream such that the visibility stream indicates, for each bin of the plurality of bins, which primitives are visible in the bin. Then, for at least one bin of the plurality of bins, each primitive in the bin that is indicated in the visibility stream as being visible in the bin is rendered.

公开(公告)号：US20170161863A1

公开(公告)日：2017-06-08

申请号：US14958911

申请日：2015-12-03

Applicant: QUALCOMM Incorporated

Inventor： Siddhartha Baral ,  Avinash Seetharamaiah ,  Christopher Paul Frascati

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/80

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/80 ,  G06T2210/12 ,  G06T2210/52

Abstract: This disclosure is directed to graphics data storage. A graphics processing unit (GPU) may determine pixels of a tile for which the GPU generated graphics data during the rendering of the tile. The GPU may store the generated graphics data in a local memory, and use the information of the pixels of the tile for which the GPU generated graphics data to limit the amount of graphics data stored in the local memory that the GPU is to write to an external memory.