公开(公告)号：US11978151B2

公开(公告)日：2024-05-07

申请号：US17823948

申请日：2022-08-31

Applicant: QUALCOMM Incorporated

Inventor： Adimulam Ramesh Babu ,  Srihari Babu Alla ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar

IPC: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T1/20 ,  G06T1/60 ,  G06T17/005 ,  G06T2210/12

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may obtain an indication of a BVH structure including a plurality of nodes, wherein the BVH structure is associated with geometry data for a plurality of primitives in a scene, wherein each of the plurality of nodes is associated with one or more primitives, where a first level BVH includes a set of first nodes and a second level BVH includes a set of second nodes. The apparatus may also allocate information for a plurality of second nodes in the set of second nodes to at least one first node in the set of first nodes. Further, the apparatus may store the allocated information for the plurality of second nodes in the set of second nodes in the at least one first node in the set of first nodes.

公开(公告)号：US11893677B1

公开(公告)日：2024-02-06

申请号：US17816375

申请日：2022-07-29

Applicant: QUALCOMM Incorporated

Inventor： Adimulam Ramesh Babu ,  Srihari Babu Alla ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar ,  David Kirk McAllister

IPC: G06T15/06 ,  G06T17/10 ,  G06T17/00 ,  G06T15/08

CPC classification number: G06T15/06 ,  G06T15/08 ,  G06T17/005 ,  G06T17/10

Abstract: Systems and techniques are provided for widening a hierarchical structure for ray tracing. For instance, a process can include obtaining a plurality of primitives of a scene object included in a first hierarchical acceleration data structure and determining one or more candidate hierarchical acceleration data structures each including the plurality of primitives. A cost metric can be determined for the one or more candidate hierarchical acceleration data structures and, based on the cost metric, a compressibility prediction associated with a candidate hierarchical acceleration data structure of the one or more candidate hierarchical acceleration data structures can be determined. An output hierarchical acceleration data structure can be generated based on the compressibility prediction.

公开(公告)号：US11682109B2

公开(公告)日：2023-06-20

申请号：US17073218

申请日：2020-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kalyan Kumar Bhiravabhatla ,  Krishnaiah Gummidipudi ,  Ankit Kumar Singh ,  Andrew Evan Gruber ,  Pavan Kumar Akkaraju ,  Srihari Babu Alla ,  Jonnala Gadda Nagendra Kumar ,  Vishwanath Shashikant Nikam

IPC: G06T5/40 ,  G06T7/13 ,  G06T1/20 ,  G06T5/20 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T5/40 ,  G06T1/20 ,  G06T5/20 ,  G06T7/13 ,  G06T15/005 ,  G06T15/40

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for configurable aprons for expanded binning. Aspects of the present disclosure include identifying one or more pixel tiles in at least one bin and determining edge information for each pixel tile of the one or more pixel tiles. The edge information may be associated with one or more pixels adjacent to each pixel tile. The present disclosure further describes determining whether at least one adjacent bin is visible based on the edge information for each pixel tile, where the at least one adjacent bin may be adjacent to the at least one bin.

公开(公告)号：US11600002B2

公开(公告)日：2023-03-07

申请号：US16892096

申请日：2020-06-03

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Srihari Babu Alla ,  Kalyan Kumar Bhiravabhatla ,  Jonnala Gadda Nagendra Kumar ,  William Licea-Kane ,  Fredrick Alan Hickman

IPC: G06T7/11 ,  G06T1/60 ,  G06T1/20 ,  G06T7/136 ,  G06T5/40

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

公开(公告)号：US20220122214A1

公开(公告)日：2022-04-21

申请号：US17071888

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Thomas Edwin Frisinger ,  Richard Hammerstone ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Shangmei Yu ,  Srihari Babu Alla

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/48

Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.

公开(公告)号：US11087431B2

公开(公告)日：2021-08-10

申请号：US16694956

申请日：2019-11-25

Applicant: QUALCOMM Incorporated

Inventor： Srihari Babu Alla ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah

IPC: G06T15/00 ,  G06T1/20 ,  G06F11/30

Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a state for each graphics state group of a plurality of graphics state groups. Further, aspects of the present disclosure can determine whether at least one graphics state group of the plurality of graphics state groups includes a changed state. Additionally, aspects of the present disclosure can communicate state information for the at least one graphics state group when the at least one graphics state group includes a changed state. In some aspects, the state information includes information regarding the state of the at least one graphics state group. Aspects of the present disclosure can also configure a draw state for the plurality of graphics state groups, where the draw state includes state information for each of the graphics state groups.

公开(公告)号：US11727631B2

公开(公告)日：2023-08-15

申请号：US17482296

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Matthew Netsch ,  Srihari Babu Alla ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar

IPC: G06T15/80 ,  G06T15/00 ,  G06T9/00 ,  G06T7/90 ,  G06T11/00 ,  G09G5/02 ,  H04N1/60

CPC classification number: G06T15/80 ,  G06T7/90 ,  G06T9/00 ,  G06T15/005

Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may perform a color analysis on at least one first frame of a plurality of frames, the color analysis being performed based on at least one image in the at least one first frame. The apparatus may also generate a frequency map for at least one second frame of the plurality of frames based on the performed color analysis. Further, the apparatus may render the at least one second frame based on the frequency map for the at least one second frame, the at least one second frame being rendered after the at least one first frame.

公开(公告)号：US11321804B1

公开(公告)日：2022-05-03

申请号：US17071888

申请日：2020-10-15

Applicant: QUALCOMM Incorporated

Inventor： Thomas Edwin Frisinger ,  Richard Hammerstone ,  Jonnala Gadda Nagendra Kumar ,  Avinash Seetharamaiah ,  Shangmei Yu ,  Srihari Babu Alla

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48

Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.

公开(公告)号：US20210383545A1

公开(公告)日：2021-12-09

申请号：US16892096

申请日：2020-06-03

Applicant: QUALCOMM Incorporated

Inventor： Jian Liang ,  Andrew Evan Gruber ,  Tao Wang ,  Srihari Babu Alla ,  Kalyan Kumar Bhiravabhatla ,  Jonnala Gadda Nagendra Kumar ,  William Licea-Kane ,  Fredrick Alan Hickman

IPC: G06T7/11 ,  G06T7/136 ,  G06T5/40 ,  G06T1/60 ,  G06T1/20

Abstract: Methods, systems, and devices for graphics processing are described. A device may receive an image including a set of pixels. The device may render a first subset of pixels in each bin of a set of bins during a first rendering pass, and defer rendering a second subset of pixels and a third subset of pixels in each bin of the set of bins during the first rendering pass. The second subset of pixels may include edge pixels and the third subset of pixels may be between the first subset of pixels and the second subset of pixels. The device may render the second subset of pixels and the third subset of pixels in each bin of the set of bins during a second rendering pass based on rendering the first subset of pixels. The device may then output the image based on the first and second rendering pass.

公开(公告)号：US11145024B2

公开(公告)日：2021-10-12

申请号：US16728591

申请日：2019-12-27

Applicant: QUALCOMM Incorporated

Inventor： Balaji Calidas ,  Joshua Walter Kelly ,  Avinash Seetharamaiah ,  Jonnala Gadda Nagendra Kumar ,  Hitendra Mohan Gangani

IPC: G06T1/20 ,  G06T15/00 ,  G06N20/00 ,  G06F9/38 ,  G06N3/08 ,  G06F9/48

Abstract: Methods, systems, and devices for processing are described. A device may parse a set of layers of a deep neural network. The set of layers may be associated with a set of machine learning operations of the deep neural network. The device may determine one or more layer parameters based on the determined set of layers. In some aspects, the device may determine an execution time associated with executing a shader dispatch based on the one or more layer parameters. The device may batch the shader dispatch to a command buffer based on the execution time and process the command buffer based on the batching. The device may determine a target execution time based on an assembly time associated with the command buffer, a processing time associated with the command buffer, a frequency level associated with processing the command buffer, the one or more layer parameters, or some combination thereof.