公开(公告)号：US20250125234A1

公开(公告)日：2025-04-17

申请号：US18486970

申请日：2023-10-13

Applicant: QUALCOMM Incorporated

Inventor： Manuel ALDRETE ,  Rajneesh KUMAR ,  Zhijie WANG ,  Aniket PATIL ,  Srikanth KULKARNI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the base structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the interposer structure. A width of the bond ball portion is greater than a width of the bond wire portion.

公开(公告)号：US20250070001A1

公开(公告)日：2025-02-27

申请号：US18455439

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Hi MOON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

Abstract: A device includes a core including an upper core dielectric layer, a lower core dielectric layer, a central core dielectric layer contacting the upper core dielectric layer and the lower core dielectric layer, and a passive electronic component embedded within the central core dielectric layer. The device includes an upper laminate stack coupled to the upper core dielectric layer. The upper laminate stack includes upper metal layers and contact pads configured to electrically connect a die to the passive electronic component by way of conductive paths defined by the set of upper metal layers. The device includes a lower laminate stack coupled to a bottom surface of the lower core dielectric layer. The lower laminate stack includes lower metal layers and a set of lower dielectric layers disposed between adjacent metal layers of the set of lower metal layers.

公开(公告)号：US20230036650A1

公开(公告)日：2023-02-02

申请号：US17386278

申请日：2021-07-27

Applicant: QUALCOMM Incorporated

Inventor： Yuan LI ,  Aniket PATIL ,  Hong Bok WE ,  Abdolreza LANGARI ,  Lisha ZHANG

IPC: H01L23/60 ,  H01L21/50 ,  H01L23/522

Abstract: In an aspect, a semiconductor includes a substrate. The substrate includes a column comprising a conductive paste that passes through a plurality of metal layers, a resin sheath surrounding the column, a ground shield surrounding the resin sheath, and a plurality of sense lines. The plurality of sense lines include a first sense line that is connected to the column comprising the conductive paste and a second sense line that is connected to the ground shield. The resin comprises a dielectric material.

公开(公告)号：US20220246531A1

公开(公告)日：2022-08-04

申请号：US17164723

申请日：2021-02-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A package comprising a substrate, a first integrated device and a second integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects, a solder resist layer, and a plurality of periphery interconnects located over the solder resist layer. The first integrated device is coupled to the substrate. The second integrated device is coupled to the substrate. The second integrated device is configured to be electrically coupled to the first integrated device through the plurality of periphery interconnects.

公开(公告)号：US20220148952A1

公开(公告)日：2022-05-12

申请号：US17093954

申请日：2020-11-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Zhijie WANG ,  Joan Rey Villarba BUOT ,  Hong Bok WE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/495 ,  H01L25/00

Abstract: A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

公开(公告)号：US20220068798A1

公开(公告)日：2022-03-03

申请号：US17002615

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Hong Bok WE

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/48

Abstract: A substrate that includes at least one dielectric layer, a plurality of first interconnects located in the at least one dielectric layer, at least one photo-imageable dielectric layer coupled to the at least one dielectric layer, and a plurality of second interconnects located in the at least one photo-imageable dielectric layer. The plurality of second interconnects includes at least one pair of adjacent interconnects having a centroid to centroid distance that is less than a pitch between the pair of interconnects. The pair of adjacent interconnects may include a pair of adjacent via interconnects and/or a pair of pad interconnects. The substrate may include a coreless substrate or a cored substrate.

公开(公告)号：US20220028816A1

公开(公告)日：2022-01-27

申请号：US16936263

申请日：2020-07-22

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Marcus HSU

IPC: H01L23/00

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

公开(公告)号：US20210351145A1

公开(公告)日：2021-11-11

申请号：US16868349

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  David Fraser RAE ,  Hong Bok WE

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.

公开(公告)号：US20210104507A1

公开(公告)日：2021-04-08

申请号：US16591374

申请日：2019-10-02

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  David Fraser RAE

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498

Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.

公开(公告)号：US20200381405A1

公开(公告)日：2020-12-03

申请号：US16426160

申请日：2019-05-30

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Bernie YANG

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

Abstract: Certain aspects of the present disclosure generally relate to a chip assembly having an embedded passive device in a bottom package of a package-on-package (PoP) assembly. An example chip assembly generally includes a first package and a second package disposed above and coupled to the first package. The first package may include a redistribution layer, an integrated circuit die disposed above and coupled to the redistribution layer, and at least one reactive component disposed above the redistribution layer and coupled to the redistribution layer and the second package.