公开(公告)号：US20190067205A1

公开(公告)日：2019-02-28

申请号：US15689967

申请日：2017-08-29

Applicant: QUALCOMM Incorporated

Inventor： David Fraser RAE ,  Hong Bok WE ,  Christopher HEALY ,  Chin-Kwan KIM

IPC: H01L23/552 ,  H01L23/13 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/552 ,  H01L21/32051 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/214 ,  H01L2924/00

Abstract: A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.

公开(公告)号：US20160218064A1

公开(公告)日：2016-07-28

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  David Fraser RAE ,  Rajneesh KUMAR ,  Milind Pravin SHAH ,  Omar James BCHIR

IPC: H01L23/538 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract translation: 半导体封装可以包括具有附接到其表面的一个或多个电子部件的下基板和具有一个或多个空腔的上基板，其中上基板在与一个或多个电子元件的多个连接点处附接到下基板 装配在单个空腔内的部件或用于允许半导体封装的整体形状保持较小的每个部件的单独的腔体。 多个连接点在上基板和下基板之间提供机械和电连接，并且可以包括在其之间的焊接接头以及当被压缩以组装时产生粘合剂增强矩阵的导电填料颗粒。

公开(公告)号：US20160343651A1

公开(公告)日：2016-11-24

申请号：US14861484

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： David Fraser RAE ,  Lizabeth Ann KESER ,  Reynante Tamunan ALVARADO

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L21/768 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2224/83 ,  H01L2224/81

Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.

Abstract translation: 封装可以包括靠近具有具有互连的衬底的结构的管芯和耦合到互连件的第一部件。 模具可能面朝上或面朝下。 封装可以包括将管芯连接到结构的互连件的第一再分配层和覆盖管芯的模具化合物，以及可能的结构。

公开(公告)号：US20190341352A1

公开(公告)日：2019-11-07

申请号：US15968774

申请日：2018-05-02

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Chin-Kwan KIM ,  Jaehyun YEON ,  Manuel ALDRETE ,  David Fraser RAE

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L21/3105 ,  H01L23/29

Abstract: A semiconductor package comprises a substrate, a die mounted on the substrate, and a mold formed over the die and on the substrate, the mold having a top surface and a plurality of tapered side surfaces, wherein the tapered side surfaces provide uniform thickness of an electromagnetic interference (EMI) shielding film.

公开(公告)号：US20170271289A1

公开(公告)日：2017-09-21

申请号：US15072315

申请日：2016-03-16

Applicant: QUALCOMM Incorporated

Inventor： Lizabeth Ann KESER ,  David Fraser RAE ,  Reynante Tamunan ALVARADO

IPC: H01L23/00 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13024 ,  H01L2224/13147 ,  H01L2924/01047 ,  H01L2924/1433 ,  H01L2924/18162 ,  H01L2924/3511

Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.

公开(公告)号：US20160343635A1

公开(公告)日：2016-11-24

申请号：US14859316

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： David Fraser RAE ,  Lizabeth Ann KESER ,  Reynante Tamunan ALVARADO

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L25/16 ,  H01L21/311 ,  H01L21/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/75 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2224/83

Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.

Abstract translation: 可以通过在制造期间在模具化合物中产生空腔，通过在靠近附接的模具的部件以模具正面朝向制造集成封装。 在底部形成有一个粘合剂层，以保持一个部件，使得部件的顶部表面与所附着的管芯的顶部表面共面。 这可能允许进行不会损坏部件的背面研磨，因为附接的模具和部件之间的顶部表面对准防止空腔的深度延伸到被剥离的包装的部分中。

公开(公告)号：US20220013472A1

公开(公告)日：2022-01-13

申请号：US16925217

申请日：2020-07-09

Applicant: QUALCOMM Incorporated

Inventor： Jeahyeong HAN ,  David Fraser RAE ,  Rajneesh KUMAR

IPC: H01L23/552 ,  H01L23/64 ,  H01L23/31

Abstract: Packages are configured to include an electromagnetic interference (EMI) shield. According to one example, a package includes a substrate, an electrical component, and an EMI shield. The substrate includes a first surface and a second surface. The electrical component may be coupled to the first side of the substrate. The EMI shield is formed with at least one passive device. The at least one passive device is coupled to the first surface of the substrate. The at least one passive device is located laterally to the at least one electrical component, and extends along at least a portion of the electrical component. Other aspects, embodiments, and features are also included.

公开(公告)号：US20210351145A1

公开(公告)日：2021-11-11

申请号：US16868349

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  David Fraser RAE ,  Hong Bok WE

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package that includes a first redistribution portion, a second redistribution portion, a third redistribution portion, a first encapsulation layer coupled to the first redistribution portion and the third redistribution portion, a first discrete device encapsulated by the first encapsulation layer, wherein the first discrete device is located between the first redistribution portion and the third redistribution portion, a second encapsulation layer coupled to the first redistribution portion and the second redistribution portion, and a second discrete device encapsulated by the second encapsulation layer, wherein the second discrete device is located between the first redistribution portion and the second redistribution portion.

公开(公告)号：US20210249325A1

公开(公告)日：2021-08-12

申请号：US16789272

申请日：2020-02-12

Applicant: QUALCOMM Incorporated

Inventor： David Fraser RAE ,  John HOLMES ,  Marcus HSU ,  Kuiwon KANG ,  Avantika SODHI

IPC: H01L23/367 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L23/42

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

公开(公告)号：US20210104507A1

公开(公告)日：2021-04-08

申请号：US16591374

申请日：2019-10-02

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  David Fraser RAE

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498

Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.