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公开(公告)号:US20240274516A1
公开(公告)日:2024-08-15
申请号:US18168420
申请日:2023-02-13
发明人: Joan Rey Villarba BUOT , Zhijie WANG , Hong Bok WE , Sang-Jae LEE
IPC分类号: H01L23/498 , H01L23/29 , H01L23/373
CPC分类号: H01L23/49816 , H01L23/293 , H01L23/3737
摘要: Disclosed are apparatuses and methods for fabricating the apparatuses. In an aspect, an apparatus may include: an interposer including a first metal layer, a second metal layer, a plurality of vias configured to thermally and electrically couple the first metal layer and the second metal layer, and a plurality of solder resist posts disposed on a bottom surface portion of the second metal layer; a package substrate; a die electrically coupled to the package substrate; and a thermal interface material (TIM) disposed on the die, where the TIM is configured to thermally coupled the die and the bottom surface portion of the second metal layer.
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公开(公告)号:US20240105568A1
公开(公告)日:2024-03-28
申请号:US17951601
申请日:2022-09-23
IPC分类号: H01L23/498 , H01L21/48 , H01L23/00 , H01L25/16
CPC分类号: H01L23/49822 , H01L21/4857 , H01L21/486 , H01L23/49816 , H01L23/49838 , H01L23/49894 , H01L24/16 , H01L25/16 , H01L2224/16227 , H01L2924/19041 , H01L2924/19042
摘要: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of interconnects located in the first dielectric layer, the second dielectric layer and the third dielectric layer. The second dielectric layer is located between the first dielectric layer and the third dielectric layer. The second dielectric layer includes a different material than the first dielectric layer and the third dielectric layer.
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公开(公告)号:US20230018448A1
公开(公告)日:2023-01-19
申请号:US17375676
申请日:2021-07-14
IPC分类号: H01L23/48 , H01L25/065 , H01L23/532 , H01L23/528 , H01L21/768 , H01L27/108
摘要: Disclosed are apparatus comprising a substrate and techniques for fabricating the same. The substrate may include a first metal layer having signal interconnects on a first side of the substrate. A second metal layer may include ground plane portions on a second side of the substrate. Conductive channels may be formed in the substrate and coupled to the ground plane portions. The conductive channels are configured to extend the ground plane portions towards the signal interconnects to reduce a distance from individual signal interconnects to individual conductive channels. The distance may be in a range of seventy-five percent to fifty percent of a substrate thickness between the first metal layer and the second metal layer.
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公开(公告)号:US20220384328A1
公开(公告)日:2022-12-01
申请号:US17334610
申请日:2021-05-28
发明人: Kuiwon KANG , Hong Bok WE , Chin-Kwan KIM , Milind SHAH
IPC分类号: H01L23/498 , H01L23/00 , H01L21/48
摘要: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.
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公开(公告)号:US20220320016A1
公开(公告)日:2022-10-06
申请号:US17223947
申请日:2021-04-06
IPC分类号: H01L23/58 , H01L23/498 , H01L23/48 , H01L23/04 , H05K1/02
摘要: In an aspect, an apparatus includes a package. The package includes a substrate, a plurality of components located on a top surface of the substrate, a plurality of ball pads located on a bottom surface of the substrate, a plurality of balls, and a plurality of test pads located on the bottom surface of the substrate. Individual balls of the plurality of balls are attached to individual ball pads of the plurality of ball pads.
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6.
公开(公告)号:US20220246496A1
公开(公告)日:2022-08-04
申请号:US17164729
申请日:2021-02-01
发明人: Hong Bok WE , Marcus HSU , Aniket PATIL
IPC分类号: H01L23/48 , H01L23/00 , H01L21/768
摘要: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.
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公开(公告)号:US20220223529A1
公开(公告)日:2022-07-14
申请号:US17148367
申请日:2021-01-13
发明人: Joan Rey Villarba BUOT , Aniket PATIL , Zhijie WANG , Hong Bok WE
IPC分类号: H01L23/538 , H01L23/00 , H01L21/48
摘要: A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.
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公开(公告)号:US20210407919A1
公开(公告)日:2021-12-30
申请号:US16915199
申请日:2020-06-29
发明人: Aniket PATIL , Hong Bok WE , Brigham NAVAJA
IPC分类号: H01L23/538 , H01L23/31 , H01L23/00 , H01L21/48 , H01L21/56
摘要: Conventional package problems may be overcome with a hybrid metallization and laminate structure that avoids warpage problems and size reduction problems. One example structure may include a metallization structure directly attached to an active side of a logic die stack in a core substrate (on one or both sides of the substrate) with laminate layers built-up on top of the metallization structures for a symmetrical package structure.
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公开(公告)号:US20210175178A1
公开(公告)日:2021-06-10
申请号:US16704378
申请日:2019-12-05
发明人: Hong Bok WE , Aniket PATIL , Kuiwon KANG , Zhijie WANG
IPC分类号: H01L23/538 , H01L23/31 , H01L23/00 , H01L21/683 , H01L21/48 , H01L21/56
摘要: A package comprising a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.
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公开(公告)号:US20210028539A1
公开(公告)日:2021-01-28
申请号:US16520140
申请日:2019-07-23
摘要: Methods and apparatuses for enhancing antenna modules with flexible portion are presented. An apparatus includes an antenna module having a first portion, a first antenna on the first portion, a second portion, a second antenna on the second portion, and a flexible portion physically connecting the first portion and the second portion. The flexible portion is arrangeable such that the first antenna and the second antenna are oriented to receive radio frequency signals from different directions or to transmit the radio frequency signals to different directions. At least one radio frequency integrated circuit is on the first portion. The first antenna and the second antenna, via the flexible portion, share the radio frequency integrated circuit for radio frequency signal transmission or reception.
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