公开(公告)号：US08009174B2

公开(公告)日：2011-08-30

申请号：US11908965

申请日：2006-03-15

申请人： Aleksandar Beric ,  Ramanathan Sethuraman

发明人： Aleksandar Beric ,  Ramanathan Sethuraman

IPC分类号： G09G5/39 ,  G06F13/18

CPC分类号： G11C8/04 ,  G06T1/60 ,  H04N19/426 ,  H04N19/433

摘要： A data buffering device which contains an input unit adapted to sequentially receive a two-dimensional array of data structures organized by an index pair with a first index stepwise traversing first-index values in a meandering manner defined by a first and a second meandering direction. The invention further includes a data buffering method, and a data processing method and device; each of which incorporates the above described features of the data buffering device.

摘要翻译： 一种数据缓冲装置，其包含输入单元，该输入单元适于顺序地接收由索引对组织的数据结构的二维阵列，其中第一索引以由第一和第二曲折方向限定的曲折方式逐步遍历第一索引值。 本发明还包括数据缓冲方法和数据处理方法和装置; 其中的每一个都包含数据缓冲装置的上述特征。

公开(公告)号：US20100088475A1

公开(公告)日：2010-04-08

申请号：US12442594

申请日：2007-09-21

申请人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Ramanathan Sethuraman

IPC分类号： G06F12/00

CPC分类号： G06T1/20 ,  G06F12/0207 ,  G06T1/60

摘要： A data processing circuit comprises an instruction execution circuit (14) and a plurality of memory banks. The instruction execution circuit (14) is capable of processing blocks of data values (e.g. pixel values for a two-dimensional block of pixels) in parallel. The data values are stored (preferably cached) in the memory banks and supplied in parallel. A plurality of translation circuits (22) is coupled between block addressing outputs of the instruction execution circuits and address inputs of the memory banks. The translation circuits provide for the possibilty of addressing more than one block in parallel from different memory banks. The data is routed to the execution circuit from the selected memory banks by routing circuits. In an embodiment each translation circuit is able to address all memory of the banks. In another embodiment the translation circuits support a plurality of ways of distributing a data of a pixel image over the memory banks, using only a few banks for example for data that is accessed in small blocks and more banks for data that accessed with higher parallelism.

摘要翻译： 数据处理电路包括指令执行电路（14）和多个存储体。 指令执行电路（14）能够并行地处理数据值块（例如，二维像素块的像素值）。 数据值被存储（优选地高速缓存）在存储体中并且并行提供。 多个平移电路（22）耦合在指令执行电路的块寻址输出和存储体的地址输入之间。 翻译电路提供了从不同的存储体并行寻址多于一个块的可能性。 数据通过路由电路从选定的存储体路由到执行电路。 在一个实施例中，每个平移电路能够寻址银行的所有存储器。 在另一个实施例中，翻译电路支持多个方式，通过仅使用少量的存储体来存储像素图像在存储器组中的数据，例如对于以小块进行访问的数据，以及用于以较高并行度访问的数据的更多存储体。

公开(公告)号：US20080282038A1

公开(公告)日：2008-11-13

申请号：US11568004

申请日：2005-04-21

申请人： Ramanathan Sethuraman ,  Aleksandar Beric ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Patrick Peter Elizabeth Meuwissen ,  Srinivasan Balakrishnan ,  Gerard Veldman

发明人： Ramanathan Sethuraman ,  Aleksandar Beric ,  Carlos Antonio Alba Pinto ,  Harm Johannes Antonius Maria Peters ,  Patrick Peter Elizabeth Meuwissen ,  Srinivasan Balakrishnan ,  Gerard Veldman

IPC分类号： G06F12/00

CPC分类号： H04N19/433 ,  G06F12/00 ,  G06F12/0862 ,  G06F12/126 ,  G06F2212/455 ,  G06F2212/6022 ,  G06F2212/6024

摘要： An array of data values, such as an image of pixel values, is stored in a main memory (12). A processing operation is performed using the pixel values. The processing operation defines time points of movement of a multidimensional region (20, 22) of locations in the image. Pixel values from inside and around the region are cached for processing. At least when a cache miss occurs for a pixel value from outside the region, cache replacement of data in cache locations (142) is performed. Locations that store pixel data for locations in the image outside the region (20, 22) are selected for replacement, selectively exempting from replacement cache locations (142) that store pixel data locations in the image inside the region. In embodiments, different types of cache structure are used for caching data values inside and outside the region. In an embodiment the cache locations for pixel data inside the regions support a higher level of output parallelism than the cache locations for pixel data around the region. In a further embodiment the cache for locations inside the region contains sets of banks, each set for a respective line from the image, data from the lines being distributed in a cyclically repeating fashion over the banks.

摘要翻译： 诸如像素值的图像的数据值阵列存储在主存储器（12）中。 使用像素值执行处理操作。 处理操作定义图像中位置的多维区域（20,22）的移动时间点。 内部和周围区域的像素值被缓存进行处理。 至少当从区域外的像素值发生高速缓存未命中时，执行高速缓存位置（142）中的数据的高速缓存替换。 选择存储用于区域（20,22）以外的图像中的位置的像素数据的位置用于替换，以选择性地免除存储区域内的图像中的像素数据位置的替换高速缓存位置（142）。 在实施例中，不同类型的高速缓存结构被用于缓存区域内外的数据值。 在一个实施例中，区域内的像素数据的高速缓存位置支持比围绕该区域的像素数据的高速缓存位置更高级的输出并行性。 在另一实施例中，区域内的高速缓冲存储器包含一组存储体，每个存储体集合用于来自图像的相应行，来自行的数据以循环重复的方式分布在存储体上。

公开(公告)号：US20080147980A1

公开(公告)日：2008-06-19

申请号：US11815981

申请日：2006-02-13

申请人： Harm Johannes Antonius Maria Peters ,  Ramanathan Sethuraman ,  Gerard Veldman ,  Patrick Peter Elizabeth Meuwissen

发明人： Harm Johannes Antonius Maria Peters ,  Ramanathan Sethuraman ,  Gerard Veldman ,  Patrick Peter Elizabeth Meuwissen

IPC分类号： G06F12/08

CPC分类号： H04N19/433 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/6022 ,  G06T7/20 ,  G06T2200/28 ,  G09G5/395 ,  G09G2320/0261 ,  G09G2360/121 ,  H04N19/436

摘要： The present invention relates to a data processing device (10) comprising a processing unit (12) and a memory unit (14), and to a method for controlling operation of a memory unit (14) of a data processing device. The memory unit (14) comprises a main memory (16), a low- level cache memory (20.2), which is directly connected to the processing unit (12) and adapted to hold all pixels of a currently active sliding search area for reading access by the processing unit (12), a high-level cache memory (18), which is connected between the low-level cache memory and the frame memory, and a first pre-fetch buffer (20.1), which is connected between the high-level cache memory and the low- level cache memory and which is adapted to hold one search-area column or one search-area line of pixel blocks, depending on the scan direction and scan Reading and fetching functionalities are decoupled in the memory unit (14). The fetching functionality is concentrated on the higher cache level, while the reading functionality is concentrated on the lower cache level. This way concurrent reading and fetching can be achieved, thus enhancing the performance of a data processing device.

摘要翻译： 本发明涉及包括处理单元（12）和存储单元（14）的数据处理设备（10），以及用于控制数据处理设备的存储单元（14）的操作的方法。 存储单元（14）包括主存储器（16），低级高速缓存存储器（20.2），其直接连接到处理单元（12）并且适于保持当前活动的滑动搜索区域的所有像素用于读取 处理单元（12）的访问，连接在低级缓存存储器和帧存储器之间的高级缓存存储器（18）和第一预取缓冲器（20.1），其连接在 高级缓存存储器和低级高速缓存存储器，其适于保持一个搜索区域列或一个搜索区域的像素块行，这取决于扫描方向和扫描读取和取出功能在存储器单元中去耦 （14）。 获取功能集中在较高的缓存级别，而读取功能集中在较低的缓存级别。 这样可以实现并行读取和取出，从而提高数据处理设备的性能。

公开(公告)号：US20060095715A1

公开(公告)日：2006-05-04

申请号：US10540698

申请日：2003-12-03

申请人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

发明人： Balakrishnan Srinivasan ,  Ramanathan Sethuraman ,  Carlos Alba Pinto ,  Harm Johannes Peters

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3853

摘要： The invention relates to a very long instruction word (VLIW) processor comprising a plurality of functional units (110, 130, 135), each for executing an operation, and a VLIW controller (100) connected to each of said functional units (110, 130, 135) and adapted to controlling said functional units (110, 130, 135). The VLIW processor comprises at least one indication means (140) associated with one of said functional units (135) and adapted to registering and indicating to the VLIW controller (100) whether said one functional unit (135) is idle or operating.

摘要翻译： 本发明涉及一种非常长的指令字（VLIW）处理器，它包括多个用于执行操作的功能单元（110,130,135），和连接到每个所述功能单元（110,130,135）的VLIW控制器（100） 130,135），并适于控制所述功能单元（110,130,135）。 所述VLIW处理器包括与所述功能单元（135）之一相关联的至少一个指示装置（140），并且适于向VLIW控制器（100）注册和指示所述一个功能单元（135）是空闲还是操作。

公开(公告)号：US20180165210A1

公开(公告)日：2018-06-14

申请号：US15373682

申请日：2016-12-09

申请人： Ramanathan Sethuraman

发明人： Ramanathan Sethuraman

IPC分类号： G06F12/0875 ,  G06F12/0891 ,  G06F12/0842 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/30021 ,  G06F9/30145 ,  G06F11/34 ,  G06F12/0842 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/62 ,  Y02D10/34

摘要： In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a number of executions of the instruction during execution of code including the instruction; and at least one comparator circuit to compare a count value from one of the plurality of entries to a threshold value, where the instruction is a tagged instruction of the code, the tagged instruction tagged by a static compiler prior to execution of the code. Other embodiments are described and claimed.

公开(公告)号：US07861062B2

公开(公告)日：2010-12-28

申请号：US10561454

申请日：2004-06-22

申请人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

发明人： Carlos Antonio Alba Pinto ,  Balakrishnan Srinivasan ,  Ramanathan Sethuraman

IPC分类号： G06F9/30

CPC分类号： G06F9/3826 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/152

摘要： The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.

摘要翻译： 数据处理装置具有多个功能单元并在连续的指令周期中发出指令。 第一种类型的说明每次都用于一个功能单元。 第二类型的指令使得功能单元的组合在相同的指令执行周期中作出响应，这是由另一个功能单元作为执行相同指令的一部分使用的结果。 优选地，该设备支持多个不同指令周期速率的替代操作，取决于所执行的程序段是否包含第二类型的指令。 最快的指令周期速率不允许执行第二种指令，因为不同功能单元的操作不符合指令执行周期。 如果可能，设备通过切换到较慢的时钟速率来节省功率，在这种情况下，通过减少必须发出的指令数量来执行第二种类型的指令以节省额外的功率。

公开(公告)号：US20080215644A1

公开(公告)日：2008-09-04

申请号：US11908965

申请日：2006-03-15

申请人： Aleksandar Beric ,  Ramanathan Sethuraman

发明人： Aleksandar Beric ,  Ramanathan Sethuraman

IPC分类号： G06F12/02 ,  G06F17/30

CPC分类号： G11C8/04 ,  G06T1/60 ,  H04N19/426 ,  H04N19/433

摘要： The present invention relates to a data buffering device (600) particularly suited for use in a data processing device (700), which sequentially provides a two-dimensional array of data structures in a meandering manner. The data buffering device (600) comprises a circular buffer memory having a number of memory locations and a buffer-control unit, which is adapted to assign to an index pair of a current incoming data structure a write-pointer value from a pointer-value set in a periodical manner one write-pointer assignment period having -a first write-pointer assignment phase, during which the first index stepwise traverses the first index-value set in the first stepwise traverses pointer values in a first rotation direction defined within the pointer-value set, -a second write-pointer assignment phase, during which the first index value stepwise traverses the first index-value set in the second meandering direction, and the write pointer stepwise traverses pointer values in the first rotation direction, -a third write-pointer assignment phase, during which the first index stepwise traverses the first index-value set in the first meandering direction, and the write pointer stepwise traverses pointer values in a second rotation direction opposite to the first rotation direction, and a fourth write-pointer assignment phase, during which the first index value stepwise traverses the first index-value set in the second meandering direction, and the write pointer value stepwise traverses pointer values in the second rotation direction. The invention is particularly useful in the field of video processing, where a motion estimator provides a two-dimensional array of motion vectors in a meandering manner, which is used by a motion compensator having a non-meandering scan order

摘要翻译： 本发明涉及一种特别适用于数据处理设备（700）的数据缓冲设备（600），其以蜿蜒的方式依次提供数据结构的二维阵列。 数据缓冲装置（600）包括具有多个存储器位置的循环缓冲存储器和缓冲器控制单元，该缓冲器控制单元适于从当前输入数据结构的指针值分配来自指针值的写指针值 以定期方式设置一个写指针分配周期，其具有第一写指针分配阶段，在该写指针分配周期期间，第一指数逐步遍历在第一阶段中设置的第一索引值，在指针内定义的第一旋转方向上遍历指针值 - 值集合， - 第二写指针分配阶段，在该第二写指针分配阶段期间，第一索引值逐步遍历在第二曲折方向中设置的第一索引值，并且写指针逐步遍历第一旋转方向上的指针值， - 第三 写指针分配阶段，其中第一索引逐步遍历第一曲折方向中设置的第一索引值，并且写指针逐步遍历尖点 r值与第一旋转方向相反的第二旋转方向，以及第四写指针分配阶段，在该第四写指针分配阶段期间，第一指标值逐步横穿第二曲折方向设置的第一指标值，并且写指针值逐步横移 第二旋转方向上的指针值。 本发明在视频处理领域特别有用，其中运动估计器以曲折的方式提供运动矢量的二维阵列，由具有非曲折扫描顺序的运动补偿器使用

公开(公告)号：US20080204602A1

公开(公告)日：2008-08-28

申请号：US11911021

申请日：2006-03-30

申请人： Aleksandar Beric ,  Ramanathan Sethuraman

发明人： Aleksandar Beric ,  Ramanathan Sethuraman

IPC分类号： H04N5/14

CPC分类号： H04N19/436 ,  H04N19/433 ,  H04N19/56

摘要： The present invention relates to the field of motion estimation in video processing. Specifically, the invention relates to a video-processing method and device for ascertaining motion vectors for a plurality of first pixel blocks forming a currently processed image region of a currently processed image of an image sequence. The invention addresses the problem of the impact of borders between neighboring image regions in region-based motion estimation on the quality of the video output in video applications like picture-rate up conversion. The video-processing device (100) of the invention comprises a processing unit (104), which is adapted to perform motion estimation on an image according to a fragmentation of the image into a number of image regions, each image a region containing the pixel blocks shared by a first number of pixel-block lines and a second number of pixel-block columns in accordance with an adjustable value of an aspect ratio of the image region, and to set a different aspect-ratio value for processing a next image of the image sequence, such that the number of image regions per image remains constant. The dynamic change of the aspect ratio of the image regions implemented in the motion estimation device of the invention reduces the impact of the borders between neighboring image regions and thus improves the quality of region-based motion estimation.

摘要翻译： 本发明涉及视频处理中的运动估计领域。 具体地，本发明涉及一种用于确定形成图像序列的当前处理图像的当前处理图像区域的多个第一像素块的运动矢量的视频处理方法和装置。 本发明解决了基于区域的运动估计中的相邻图像区域之间的边界对视频输出在质量上的影响的问题，例如图像比率上变换。 本发明的视频处理装置（100）包括处理单元（104），该处理单元（104）适于根据图像的分段对图像执行运动估计到多个图像区域，每个图像包含像素的区域 根据图像区域的宽高比的可调整值，由第一数量的像素块行和第二数量的像素块列共享的块，并且设置用于处理图像区域的下一个图像的不同宽高比值 图像序列，使得每个图像的图像区域的数量保持不变。 在本发明的运动估计装置中实现的图像区域的纵横比的动态变化减小了相邻图像区域之间的边界的影响，从而提高了基于区域的运动估计的质量。

公开(公告)号：US20080192827A1

公开(公告)日：2008-08-14

申请号：US11910997

申请日：2006-04-04

申请人： Aleksander Beric ,  Ramanathan Sethuraman

发明人： Aleksander Beric ,  Ramanathan Sethuraman

IPC分类号： H04N7/12

CPC分类号： H04N5/145 ,  H04N19/433 ,  H04N19/56

摘要： The present invention relates to the field of motion estimation in video processing. Specifically the invention relates to a video-processing method and device for ascertaining motion vectors for a plurality of first pixel blocks forming a currently processed image region of a currently processed image of an image sequence. The invention addresses the problem of the impact of region-based motion estimation on the quality of the video output in video applications like picture-rate up conversion. The video-processing device of the invention comprises a processing unit, which is adapted to ascertain motion vectors for a plurality of first pixel blocks (C), which form a currently processed image region (200.1 to 200.14) of a currently processed image (200) of an image sequence, proceeding from image region to image region and processing a respective image region at least twice before proceeding to a next image region. Ascertaining a motion vector for a currently processed first pixel block (C) of the image region is performed by evaluating a respective set of candidate motion vectors containing at least one temporal candidate vector, which is a motion vector that was ascertained for a second pixel block (T) of a preceding image of the image sequence. The video-processing device of the invention is adapted to update, before processing a respective image region (200.2) of the currently processed image a second time, a temporal candidate vector, which was ascertained for a third pixel block located outside the currently processed image region (200.2) in the preceding image, by ascertaining a motion vector for the third pixel block (216) in the currently processed image and replacing the temporal candidate vector with it. By updating temporal motion vector candidates assigned to pixel blocks located outside the currently processed region in a first motion estimation pass, the quality of a motion estimation algorithm after the second or further motion estimation pass is improved in comparison with prior-art solutions.