公开(公告)号：US20050229127A1

公开(公告)日：2005-10-13

申请号：US10816799

申请日：2004-04-02

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: The present invention is directed to methods for verifying adequate synchronisation of signals that cross clock environments. According to one exemplary method, a circuit under design includes a plurality of functional elements and a plurality of clock environments, and has one or more signals passing from one clock environment to another therein. The method includes the steps of (i) modelling at least one of the functional elements to have an unknown state as an output for a predetermined time after a timing event of a clock signal, (ii) simulating the circuit, and (iii) determining which functional element is a synchroniser to thereby identify if there is a synchronisation problem for a signal passing from one clock environment to another.

Abstract translation: 本发明涉及用于验证跨时钟环境的信号的充分同步的方法。 根据一个示例性方法，设计中的电路包括多个功能元件和多个时钟环境，并且具有从一个时钟环境到另一个时钟环境的一个或多个信号。 该方法包括以下步骤：（i）在时钟信号的定时事件，（ii）模拟电路之后的预定时间内将功能元件中的至少一个功能元件建模为具有未知状态作为输出，以及（iii）确定 哪个功能元件是同步器，从而识别对于从一个时钟环境传递到另一个时钟环境的信号是否存在同步问题。

公开(公告)号：US20050212144A1

公开(公告)日：2005-09-29

申请号：US10809720

申请日：2004-03-25

Applicant: William Rugg ,  Robert Warren ,  Chau-Chin Low

Inventor： William Rugg ,  Robert Warren ,  Chau-Chin Low

IPC: H01L25/065 ,  H01L25/18 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2924/14 ,  H01L2924/00012

Abstract: Disclosed is a method and apparatus for stacking dice including multi-chip packaging with additional non stacked dice. The stacked dice have at least one electrical connection located on a single surface and oriented in the same direction when stacked. These dice are stacked, offset and coupled electrically. In an embodiment, the stacked dice have a buffer function, such as an SDRAM device, and are included in a multi-chip package (MCP) with an additional die including a channel function and a controller function thereon. The dice are packaged in a single package for placement on a printed circuit board for use in a storage device such as a disc drive.

Abstract translation: 公开了一种用于堆叠包括多芯片封装的骰子的附加非堆叠骰子的方法和装置。 堆叠的骰子具有位于单个表面上的至少一个电连接并且在堆叠时朝向相同的方向。 这些骰子堆叠，偏移和电耦合。 在一个实施例中，堆叠的骰子具有诸如SDRAM装置的缓冲功能，并且被包括在具有附加管芯的多芯片封装（MCP）中，该芯片包括通道功能和其上的控制器功能。 骰子被封装在单个包装中以放置在印刷电路板上用于诸如盘驱动器的存储装置中。

公开(公告)号：US20050166106A1

公开(公告)日：2005-07-28

申请号：US11015749

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/3187 ,  G01R31/28

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：US06430727B1

公开(公告)日：2002-08-06

申请号：US08994534

申请日：1997-12-19

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F1750

CPC classification number: G06F11/3648

Abstract: A single chip integrated circuit device includes a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes. The breakpoint range unit further has comparison logic operative to compare the contents of the address register with each of a lower and upper breakpoint address, and to issue a breakpoint signal when the address held in an address register is equal to the lower breakpoint address or between the lower and upper breakup addresses. On chip control logic is connected to receive the breakpoint signal and arranged to interrupt normal operation of the CPU when the breakpoint signal is received. The comparison logic includes inverse state logic configured to set an inverse state indicator to cause generation of the breakpoint signal outside the address range defined by the upper and lower breakpoint address.

Abstract translation: 单芯片集成电路装置包括具有第一和第二断点寄存器的断点范围单元，用于分别保持CPU的正常操作为了诊断目的而被中断的下断点和上断点地址。 断点范围单元还具有比较逻辑，用于将地址寄存器的内容与下断点和上断点地址中的每一个进行比较，并且当保持在地址寄存器中的地址等于下断点地址时，或者在 较低和较高的分解地址。 连接芯片控制逻辑以接收断点信号，并且当接收到断点信号时被布置成中断CPU的正常操作。 比较逻辑包括反状态逻辑，其被配置为设置反向状态指示器以导致在由上部和下部断点地址定义的地址范围之外的断点信号的产生。

公开(公告)号：US6134652A

公开(公告)日：2000-10-17

申请号：US995255

申请日：1997-12-19

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F11/28 ,  G06F11/22 ,  G06F11/36 ,  G06F15/00

CPC classification number: G06F11/3648

Abstract: An on-chip breakpoint unit of an integrated circuit device is connected to receive the contents of an instruction pointer register via an address communication path. The breakpoint unit has a breakpoint register configured to hold a breakpoint address at which the normal operation of the CPU is to be interrupted for diagnostic purposes, and a comparator circuit operative to compare the breakpoint address with the contents of the instruction pointer register and to issue a breakpoint signal on a breakpoint signal path when there is a match. The on-chip breakpoint unit also has circuitry configured to inhibit generation of the breakpoint signal for a next instruction to be executed upon resumption of normal operation of the CPU after it has been interrupted.

Abstract translation: 连接集成电路器件的片上断点单元，以经由地址通信路径接收指令指针寄存器的内容。 断点单元具有断点寄存器，该断点寄存器被配置为保存要为了诊断目的而中断CPU的正常操作的断点地址，并且比较器电路用于将断点地址与指令指针寄存器的内容进行比较并发出 当有匹配时，断点信号路径上的断点信号。 片上断点单元还具有电路，其被配置为在CPU被中断之后恢复CPU的正常操作时禁止产生用于要执行的下一个指令的断点信号。

公开(公告)号：US6134481A

公开(公告)日：2000-10-17

申请号：US959697

申请日：1997-10-29

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G06F11/30 ,  G06F11/36 ,  G06F11/34

CPC classification number: G06F11/3656

Abstract: A method of effecting communication in a computer system between off-chip circuitry and on-chip circuitry is disclosed, according to a message protocol in which four messages can be formulated: a data write request; a data read request; a response message; and a diagnostic message.

Abstract translation: 根据消息协议公开了一种在片外电路和片上电路之间在计算机系统中进行通信的方法，其中可以表达四个消息：数据写入请求; 数据读取请求; 一个回应信息; 和诊断信息。

公开(公告)号：US08899145B2

公开(公告)日：2014-12-02

申请号：US13362936

申请日：2012-01-31

Applicant: Ryan T. Harrison ,  Thomas Parel ,  Robert Warren ,  Kenneth M. Brazell ,  Zachary Scott ,  Scott Kippes ,  Mark Huggins ,  Taku Ohi ,  Jason Porter Whitmire ,  Adam Clark ,  Robert McCracken ,  Christopher Clearman

Inventor： Ryan T. Harrison ,  Thomas Parel ,  Robert Warren ,  Kenneth M. Brazell ,  Zachary Scott ,  Scott Kippes ,  Mark Huggins ,  Taku Ohi ,  Jason Porter Whitmire ,  Adam Clark ,  Robert McCracken ,  Christopher Clearman

IPC: A47J37/06 ,  A47J45/00 ,  F24B15/00 ,  A47J45/10 ,  A47J37/07

CPC classification number: A47J37/067 ,  A47J37/0786 ,  A47J45/10

Abstract: A tool for removing an interchangeable cooking insert from a grill has a handle end and an engagement end. A handle extends from the handle end toward the engagement end. A support arm extends from the handle toward the engagement end. The support arm has a first lateral edge defining a first lifting hook and a second lateral edge defining a second lifting hook. The first lifting hook and second lifting hook are configured to engage a portion of the cooking insert. A support pin extends across the support arm between the first lateral edge and the second lateral edge. A latch member is pivotally coupled to one of the support arm and the handle. The latch member includes a first end selectively engageable with a portion of the cooking insert and a second end extending through the handle for actuation of the latching member by a user.

Abstract translation: 用于从烤架移除可互换烹饪插入件的工具具有手柄端和接合端。 手柄从手柄端向接合端延伸。 支撑臂从手柄向接合端延伸。 支撑臂具有限定第一提升钩的第一侧边缘和限定第二提升钩的第二侧边缘。 第一提升钩和第二提升钩构造成接合烹饪插入件的一部分。 支撑销在第一侧边缘和第二侧边缘之间延伸穿过支撑臂。 闩锁构件枢转地联接到支撑臂和手柄中的一个。 闩锁构件包括可选择性地与烹饪插入件的一部分接合的第一端和延伸穿过手柄的第二端，用于由使用者致动闩锁构件。

公开(公告)号：US08377731B2

公开(公告)日：2013-02-19

申请号：US13236532

申请日：2011-09-19

Applicant: Robert Warren

Inventor： Robert Warren

IPC: H01L21/00

CPC classification number: G01L1/146 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  G01D5/24 ,  G01L9/0072 ,  G01P15/08 ,  G01P15/0975

Abstract: A micro electro-mechanical sensor is provided. The micro electro-mechanical sensor includes a substrate, and a conducting plane disposed on the substrate. A conducting via is disposed on the substrate, such as adjacent to the conducting plane. A plurality of ribbon conductors are disposed over the conducting plane and electrically connected to the conducting via, such that the plurality of ribbon conductors form a transducer array in combination with the conducting plane, such as through capacitive coupling that changes in response to changes in the physical shape of the plurality of ribbons.

Abstract translation: 提供了微机电传感器。 微电子机械传感器包括基板和设置在基板上的导电平面。 导电通孔设置在基板上，例如与导电平面相邻。 多个带状导体设置在导电平面上并电连接到导电通孔，使得多个带状导体与导电平面组合形成换能器阵列，例如通过电容耦合，其响应于 多个色带的物理形状。

公开(公告)号：US07823649B2

公开(公告)日：2010-11-02

申请号：US12061243

申请日：2008-04-02

Applicant: Clifford D. Brown ,  Robert Warren ,  Lee Smith

Inventor： Clifford D. Brown ,  Robert Warren ,  Lee Smith

IPC: E21B33/13

CPC classification number: E21B43/123 ,  E21B33/10 ,  E21B33/13

Abstract: Plugging a side pocket mandrel using a swelling plug. A system for plugging a port in a side pocket of a mandrel in a subterranean well includes a plugging device installed in the side pocket of the mandrel, the plugging device including a swellable seal material, whereby the seal material swells at least after installation of the plugging device in the side pocket to thereby prevent fluid transfer through the port. A method of plugging a port in a side pocket of a mandrel in a subterranean well includes the steps of: providing the plugging device with a swellable seal material; installing the plugging device in the side pocket; and the seal material swelling in the side pocket, thereby preventing fluid transfer through the port.

Abstract translation: 使用膨胀塞堵塞侧袋心轴。 用于堵塞位于地下井中的心轴的侧袋中的端口的系统包括安装在心轴的侧袋中的堵塞装置，所述堵塞装置包括可膨胀的密封材料，由此密封材料至少在安装之后膨胀 堵塞装置在侧袋中，从而防止流体通过端口传递。 将地下井中心轴的侧袋中的端口堵塞的方法包括以下步骤：为堵塞装置提供可膨胀的密封材料; 将封堵装置安装在侧袋中; 并且密封材料在侧袋中膨胀，从而防止流体通过端口传递。

公开(公告)号：US20100192031A1

公开(公告)日：2010-07-29

申请号：US12657228

申请日：2010-01-15

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。